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参数资料
型号： R5F5630ADDFP#V0
厂商： Renesas Electronics America
文件页数： 140/165页
文件大小： 0K
描述： MCU RX630 768KB FLASH 100-LQFP
产品培训模块： RX Compare Match Timer
RX DMAC
标准包装： 1
系列： RX600
核心处理器： RX
芯体尺寸： 32-位
速度： 100MHz
连通性： CAN，EBI/EMI，I²C，LIN，SCI，SPI，USB
外围设备： DMA，LVD，POR，PWM，WDT
输入/输出数： 78
程序存储器容量： 768KB（768K x 8）
程序存储器类型： 闪存
RAM 容量： 96K x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
数据转换器： A/D 8x10b，14x12b，D/A 1x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 100-LQFP
包装： 托盘
R01DS0060EJ0100 Rev.1.00
Page 76 of 168
Sep 13, 2011
RX630 Group
4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP
[R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1.
This applies to the number of cycles when the access from the CPU does not conflict with the instruction
fetching to the external memory or bus access from the different bus master (DMAC or DTC).
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相关代理商/技术参数
参数描述
R5F5630ADDLC 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCUs
R5F5630ADDLC#U0 制造商:Renesas Electronics Corporation 功能描述:RX630 768KB/96KB LGA177 CAN 100MHZ - Trays
R5F5630ADDLK 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCUs
R5F5630ADDLK#U0 制造商:Renesas Electronics Corporation 功能描述:RX630 768KB/96KB LGA145 CAN 100MHZ - Trays
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