R01DS0060EJ0100 Rev.1.00
Page 123 of 168
Sep 13, 2011
RX630 Group
5. Electrical Characteristics
5.4
Clock Timing
Note 1. This is the time until the clock is used after setting P36 and P37 as inputs, and then clearing the main clock-oscillator stop bit
(MOSCCR.MOSTP) to 0 (selecting operation).
Note 2. This is the time until the frequency of oscillation by the HOCO (fHOCO) reaches the range for guaranteed operation. after
release from the reset state.
Table 5.9
Clock Timing (Except for Sub-Clock Related)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
tBcyc
40
—
ns
BCLK pin output high pulse width
tCH
5—
—
ns
BCLK pin output low pulse width
tCL
5—
—
ns
BCLK pin output rising time
tCr
——
5
ns
BCLK pin output falling time
tCf
——
5
ns
EXTAL external clock input cycle time
tEXcyc
50
—
ns
EXTAL external clock input high pulse width
tEXH
20
—
ns
EXTAL external clock input low pulse width
tEXL
20
—
ns
EXTAL external clock rising time
tEXr
——
5
ns
EXTAL external clock falling time
tEXf
——
5
ns
EXTAL external clock input wait ti
me*1tEXWT
1—
—
ms
Main clock oscillator oscillation frequency
fMAIN
4
—
16
MHz
Main clock oscillation stabilization time (crystal)
tMAINOSC
10
—
ms
Main clock oscillation stabilization wait time (crystal)
tMAINOSCWT
20
—
ms
LOCO clock cycle time
tcyc
9.4
8
6.96
s
Low-speed on-chip oscillator oscillation frequency
fLOCO
106.25
125
143.75
kHz
LOCO clock oscillation stabilization wait time
tLOCOWT
—
20
s
High-speed on-chip oscillator oscillation frequency
fHOCO
45
50
55
MHz
HOCO clock oscillation stabilization wait time
1*2tHOCOWT1
—
1.8
ms
HOCO clock oscillation stabilization wait time 2
tHOCOWT2
—
2.0
ms
HOCO clock power supply settling time
tHOCOP
—
1
ms
PLL circuit oscillation frequency
fPLL
104
—
200
MHz
PLL clock oscillation stabilization time
PLL operation started
after main clock
oscillation has settled
tPLL1
—
500
s
PLL clock oscillation stabilization wait
tPLLWT1
1.5
—
ms
PLL clock oscillation stabilization time
PLL operation started
before main clock
oscillation has settled
tPLL2
10
—
ms
PLL clock oscillation stabilization wait
tPLLWT2
11
—
ms
Table 5.10
Clock Timing (Sub-Clock Related)
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Sub-clock oscillator oscillation frequency
fSUB
—
32.768
—
kHz
Sub-clock oscillation stabilization time
tSUBOSC
2
—
s
Sub-clock oscillation stabilization wait time
tSUBOSCWT
4—
—
s