参数资料
型号: R5F5630ADDFP#V0
厂商: Renesas Electronics America
文件页数: 19/165页
文件大小: 0K
描述: MCU RX630 768KB FLASH 100-LQFP
产品培训模块: RX Compare Match Timer
RX DMAC
标准包装: 1
系列: RX600
核心处理器: RX
芯体尺寸: 32-位
速度: 100MHz
连通性: CAN,EBI/EMI,I²C,LIN,SCI,SPI,USB
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 78
程序存储器容量: 768KB(768K x 8)
程序存储器类型: 闪存
RAM 容量: 96K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x10b,14x12b,D/A 1x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
R01DS0060EJ0100 Rev.1.00
Page 115 of 168
Sep 13, 2011
RX630 Group
4. I/O Registers
○: Available, ×: Not available
000A 0098h
USB0
Pipe 3 transaction counter enable register
PIPE3TRE
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 009Ah
USB0
Pipe 3 transaction counter register
PIPE3TRN
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 009Ch
USB0
Pipe 4 transaction counter enable register
PIPE4TRE
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 009Eh
USB0
Pipe 4 transaction counter register
PIPE4TRN
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 00A0h
USB0
Pipe 5 transaction counter enable register
PIPE5TRE
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 00A2h
USB0
Pipe 5 transaction counter register
PIPE5TRN
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 0400h
USB0
Deep standby USB transceiver control/pin
monitor register
DPUSR0R
32
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
000A 0404h
USB0
Deep standby USB suspend/resume interrupt
register
DPUSR1R
32
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
007F C402h
FLASH
Flash mode register
FMODR
8
2, 3 FCLK
2, 3 ICLK
007F C410h
FLASH
Flash access status register
FASTAT
8
2, 3 FCLK
2, 3 ICLK
007F C411h
FLASH
Flash access error interrupt enable register
FAEINT
8
2, 3 FCLK
2, 3 ICLK
007F C412h
FLASH
Flash ready interrupt enable register
FRDYIE
8
2, 3 FCLK
2, 3 ICLK
007F C440h
FLASH
E2 data flash read enable register 0
DFLRE0
16
2, 3 FCLK
2, 3 ICLK
007F C442h
FLASH
E2 data flash read enable register 1
DFLRE1
16
2, 3 FCLK
2, 3 ICLK
007F C450h
FLASH
E2 data flash programming/erasure enable
register 0
DFLWE0
16
2, 3 FCLK
2, 3 ICLK
007F C452h
FLASH
E2 data flash programming/erasure enable
register 1
DFLWE1
16
2, 3 FCLK
2, 3 ICLK
007F C454h
FLASH
FCU RAM enable register
FCURAME
16
2, 3 FCLK
2, 3 ICLK
007F FFB0h
FLASH
Flash status register 0
FSTATR0
8
2, 3 FCLK
2, 3 ICLK
007F FFB1h
FLASH
Flash status register 1
FSTATR1
8
2, 3 FCLK
2, 3 ICLK
007F FFB2h
FLASH
Flash P/E mode entry register
FENTRYR
16
2, 3 FCLK
2, 3 ICLK
007F FFB4h
FLASH
Flash protection register
FPROTR
16
2, 3 FCLK
2, 3 ICLK
007F FFB6h
FLASH
Flash reset register
FRESETR
16
2, 3 FCLK
2, 3 ICLK
007F FFBAh
FLASH
FCU command register
FCMDR
16
2, 3 FCLK
2, 3 ICLK
007F FFC8h
FLASH
FCU processing switching register
FCPSR
16
2, 3 FCLK
2, 3 ICLK
007F FFCAh
FLASH
E2 data flash blank check control register
DFLBCCNT
16
2, 3 FCLK
2, 3 ICLK
007F FFCCh
FLASH
Flash P/E status register
FPESTAT
16
2, 3 FCLK
2, 3 ICLK
007F FFCEh
FLASH
E2 data flash blank check status register
DFLBCSTAT
16
2, 3 FCLK
2, 3 ICLK
007F FFE8h
FLASH
Peripheral clock notification register
PCKAR
16
2, 3 FCLK
2, 3 ICLK
Note 1.
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
Table 4.1
List of I/O Registers (Address Order) (39/39)
Address
Module
Symbol
Register Name
Register Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK
PCLK
ICLK
PCLK
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