
R01UH0218EJ0110 Rev.1.10
Page 147 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
10. Interrupts
Notes:
1.
Each entry is relative to the base address in the INTB register.
2.
Interrupts from this source cannot be disabled by the I flag.
3.
In I2C mode, interrupts are generated by NACK, ACK, or detection of a start condition/stop condition.
Table 10.2
Relocatable Vector Table (1/4)
Interrupt Source
Vector Table Relative Addresses
(Address (L) to Address (H))
(1)Software
Interrupt
Number
Reference
+0 to +3 (0000h to 0003h)
0
R32C/100 Series
Software Manual
Reserved
+4 to +7 (0004h to 0007h)
1
Reserved
+8 to +11 (0008h to 000Bh)
2
(Reserved)
Reserved
+12 to +15 (000Ch to 000Fh)
3
Reserved
+16 to +19 (0010h to 0013h)
4
Reserved
+20 to +23 (0014h to 0017h)
5
Reserved
+24 to +27 (0018h to 001Bh)
6
Reserved
+28 to +31 (001Ch to 001Fh)
7
DMA0 transfer complete
+32 to +35 (0020h to 0023h)
8
DMA1 transfer complete
+36 to +39 (0024h to 0027h)
9
DMA2 transfer complete
+40 to +43 (0028h to 002Bh)
10
DMA3 transfer complete
+44 to +47 (002Ch to 002Fh)
11
Timer A0
+48 to +51 (0030h to 0033h)
12
Timer A1
+52 to +55 (0034h to 0037h)
13
Timer A2
+56 to +59 (0038h to 003Bh)
14
Timer A3
+60 to +63 (003Ch to 003Fh)
15
Timer A4
+64 to +67 (0040h to 0043h)
16
UART0 transmission, NACK (3)
+68 to +71 (0044h to 0047h)
17
UART0 reception, ACK (3)
+72 to +75 (0048h to 004Bh)
18
UART1 transmission, NACK (3)
+76 to +79 (004Ch to 004Fh)
19
UART1 reception, ACK (3)
+80 to +83 (0050h to 0053h)
20
Timer B0
+84 to +87 (0054h to 0057h)
21
Timer B1
+88 to +91 (0058h to 005Bh)
22
Timer B2
+92 to +95 (005Ch to 005Fh)
23
Timer B3
+96 to +99 (0060h to 0063h)
24
Timer B4
+100 to +103 (0064h to 0067h)
25
INT5
+104 to +107 (0068h to 006Bh)
26
INT4
+108 to +111 (006Ch to 006Fh)
27
INT3
+112 to +115 (0070h to 0073h)
28
INT2
+116 to +119 (0074h to 0077h)
29
INT1
+120 to +123 (0078h to 007Bh)
30
INT0
+124 to +127 (007Ch to 007Fh)
31
Timer B5
+128 to +131 (0080h to 0083h)
32