
R01UH0218EJ0110 Rev.1.10
Page 162 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
10. Interrupts
Figure 10.10 Priority Resolver of the R32C/145 Group
DMA1
DMA3
Timer A1
Timer A3
UART0 transmission
UART1 transmission
Timer B0
Timer B3
INT5
INT3
INT1
Timer B5
UART2 reception
A/D converter 0
Intelligent I/O0
Intelligent I/O2
DMA2
Timer A0
Timer A2
Timer A4
UART0 reception
UART1 reception
Timer B1
INT4
INT2
INT0
UART2 transmission
Key input
Intelligent I/O1
Level 0
(default)
Oscillator stop detection
NMI
Interrupt request
accepted (to CPU)
High
Intelligent I/O4
Intelligent I/O6
Intelligent I/O8
Intelligent I/O10
Intelligent I/O3
Intelligent I/O5
Intelligent I/O7
Intelligent I/O9
Intelligent I/O11
CAN0 transmission
CAN1 transmission
CAN2 transmission
CAN0 wakeup
CAN2 wakeup
GW error
CAN0 receive FIFO/GW0
Serial bus interface 1
LIN1
CAN0 reception
CAN1 reception
CAN2 reception
CAN1 wakeup
CAN0 transmit FIFO
LIN0
Level 0
(default)
Low
Peripheral interrupt priority
(for interrupts with same request level)
CAN4 wakeup
CAN4 transmit FIFO
CAN5 transmit FIFO
UART3 transmission
UART4 transmission
LIN Low detection
CAN5 wakeup
CAN4 receive FIFO/GW4
CAN5 receive FIFO/GW5
UART3 reception
UART4 reception
Serial bus interface 0
CAN2 error
CAN1 error
CAN0 error
Watchdog timer
High
Low
CAN3 error
CAN3 transmission
CAN3 reception
CAN3 wakeup
Timer B2
DMA0
CAN1 receive FIFO/GW1
CAN1 transmit FIFO
CAN2 receive FIFO/GW2
CAN2 transmit FIFO
CAN3 receive FIFO/GW3
CAN3 transmit FIFO
CAN4 transmission
CAN4 reception
CAN4 error
CAN5 error
CAN5 transmission
CAN5 reception
Wake-up signal
from wait or stop
mode (to clock
generator)
IPL
I flag
Request level of interrupts
Bits RLVL2 to RLVL0 in
the RIPL1 register
DMA II transfer complete
UART2 start condition/
stop condition detection
Timer B4
UART0 start condition/
stop condition detection
UART1 start condition/
stop condition detection