参数资料
型号: RCPXA272FC0312
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 312 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 107/138页
文件大小: 1048K
代理商: RCPXA272FC0312
Part 2: Flash Device Operations
Flash Read Operations
70
Intel PXA27x Processor Family Memory Subsystem
10.2
Flash Synchronous Burst-Mode Read
Read Configuration register bits RCR[15:0] must be set before flash synchronous burst operation
can be performed. Synchronous burst mode can be performed for both array and non-array reads
such as Read ID, Read Status or Read Query. (See Section 10.3, “Flash Read Configuration
Register” on page 70 for details). Synchronous burst-mode outputs 4-, 8-, 16-, or continuous-
words. To perform a synchronous burst- read, an initial address is driven onto A[MAX:MIN], and
F-CE# and ADV# are asserted. WE# and F-RST# must already have been deasserted. ADV# is
asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted
throughout the burst access, in which case the address is latched on the next valid F-CLK edge
while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid F-CLK edge after the initial access latency delay (see Section 10.3.2, “Flash
Latency Count” on page 72). Subsequent data is output on valid F-CLK edges following a
minimum delay. However, for a synchronous non-array read, the same word of data will be output
on successive clock edges until the burst length requirements are satisfied.
10.2.1
Flash Burst Suspend
The Burst Suspend feature of the flash can reduce or eliminate the initial access latency incurred
when system software needs to suspend a burst sequence that is in progress in order to retrieve data
from another device on the same system bus. The PXA27x processor can resume the burst
sequence later. Burst suspend provides maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the flash has output data. When a burst access is suspended, internal array sensing continues and
any previously latched internal data are retained. A burst sequence can be suspended and resumed
without limit as long as flash operation conditions are met.
Burst Suspend occurs when F-CE# is asserted, the current address has been latched (either ADV#
rising edge or valid F-CLK edge), F-CLK is halted, and OE# is deasserted. F-CLK can be halted
when it is at VIH or VIL.
To resume the burst access, OE# is reasserted, and F-CLK is restarted. Subsequent F-CLK edges
resume the burst sequence.
10.3
Flash Read Configuration Register
The flash Read Configuration Register (RCR) is used to select the read mode (synchronous or
asynchronous), and it defines the synchronous burst characteristics of the flash. To modify RCR
settings, use the Configure Read Configuration Register command (see Section 9.2, “Flash Bus
RCR contents can be examined using the Read Device Identifier command, and then reading from
<partition base address> + 0x05 offset. See Section 15.2, “Flash Read Device Identifier” on
page 95. The RCR is shown in Table 23 on page 71.
相关PDF资料
PDF描述
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
RD151TS3314ARPH0 80 MHz, OTHER CLOCK GENERATOR, PDSO8
RD151TS3326ARPH0 80 MHz, OTHER CLOCK GENERATOR, PDSO8
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