参数资料
型号: RCPXA272FC0312
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 312 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 90/138页
文件大小: 1048K
代理商: RCPXA272FC0312
Part 1: EMTS
Power and Reset Specifications
Intel PXA27x Processor Family Memory Subsystem
55
Power and Reset Specifications
8
8.1
Flash Power-Up and Power-Down
Power supply sequencing is not required if F-VCC, VCCQ, and F-VPP are connected together. If
VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should reach
F-VCC MIN before applying VCCQ and F-VPP. Device inputs should not be driven before supply
voltage equals F-VCC MIN.
Power supply transitions should only occur when F-RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Flash Output Disable
When OE# is deasserted, the flash outputs DQ[MAX:0] are disabled and placed in Hign-Z.
8.3
Flash Standby
When F-CE# is deasserted the flash is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in High-Z, independent of the level
placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval,
5
s after F-CE# is deasserted.
When the flash is deselected (while F-CE# is deasserted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
8.4
Flash Reset
When the PXA27x processor reset occurs with no flash memory reset, improper processor
initialization may occur because the flash memory may be providing status information rather than
array data. F-RST# should be controlled by the same low-true reset signal that resets the PXA27x
processor.
After initial power-up or reset, the flash defaults to asynchronous Read Array, and the Status
Register is set to 0x80. A minimum delay is required before an initial read access or a write cycle
can be initiated. After this wake-up interval passes, normal operation is restored. See Table 17 and
Figure 23 on page 56 for details about the flash reset timing.
Note:
If F-RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data may have been only partially written or erased.
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