参数资料
型号: RCPXA273FC0416
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 416 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 102/138页
文件大小: 1048K
代理商: RCPXA273FC0416
Part 2: Flash Device Operations
Device Operations Overview
66
Intel PXA27x Processor Family Memory Subsystem
9.3
Flash Command Definitions
Table 22.
Flash Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Description
Read
0xFF Read Array
Places the addressed partition in Read Array mode. Array data is output on DQ[15:0].
0x70
Read Status
Register
Places the addressed partition in Read Status Register mode. The partition enters this
mode after a program or erase command is issued. Status Register data is output on
DQ[7:0].
0x90
Read Device ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/device codes, Configuration
Register data, Block Lock status, or Protection Register data on DQ[15:0].
0x98
Read Query
Places the addressed partition in Read Query mode. Subsequent reads from the
partition addresses output Common Flash Interface information on DQ[7:0].
0x50
Clear Status
Register
The WSM can only set Status Register error bits. The Clear Status Register command
is used to clear the SR error bits.
Write
0x40
Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write operation.
On the next write cycle, the address and data are latched and the WSM executes the
programming algorithm at the addressed location. During program operations, the
partition responds only to Read Status Register and Program Suspend commands.
F-CE# or OE# must be toggled to update the Status Register in asynchronous read.
F-CE# or ADV# must be toggled to update the Status Register Data for synchronous
Non-array read. The Read Array command must be issued to read array data after
programming has finished.
0x10
Alternate Word
Program Setup
Equivalent to the Word Program Setup command, 0x40.
0xE8
Buffered Program
This command loads a variable number of bytes up to the buffer size of 32-words onto
the program buffer.
0xD0
Buffered Program
Confirm
The confirm command is Issued after the data streaming for writing into the buffer is
done. This instructs the WSM to perform the Buffered Program algorithm, writing the
data from the buffer to the flash memory array.
0x80
Buffered Enhanced
Factory
Programming Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode
(Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0,
that initiates the Buffered EFP algorithm. All other commands are ignored when
Buffered EFP mode begins.
0xD0
Buffered EFP
Confirm
If the previous command was Buffered EFP Setup (0x80), the CUI latches the address
and data, and prepares the flash for Buffered EFP mode.
Erase
0x20
Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The
WSM performs the erase algorithm on the block addressed by the Erase Confirm
command. If the next command is not the Erase Confirm (0xD0) command, the CUI
sets Status Register bits SR.4 and SR.5, and places the addressed partition in read
status register mode.
0xD0
Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the address and
data, and the WSM erases the addressed block. During block-erase operations, the
partition responds only to Read Status Register and Erase Suspend commands. F-
CE# or OE# must be toggled to update the Status Register in asynchronous read. F-
CE# or ADV# must be toggled to update the Status Register Data for synchronous
Non-array read.
Suspend
0xB0
Program or Erase
Suspend
This command issued to any flash address initiates a suspend of the currently-
executing program or block erase operation. The Status Register indicates successful
suspend operation by setting either SR.2 (program suspended) or SR.6 (erase
suspended), along with SR.7 (ready). The Write State Machine remains in the suspend
mode regardless of control signal states (except for F-RST# asserted).
0xD0
Suspend Resume
This command issued to any flash address resumes the suspended program or block-
erase operation.
相关PDF资料
PDF描述
RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
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