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参数资料
型号： RCPXA273FC0416
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 416 MHz, MICROPROCESSOR, PBGA336
封装： 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数： 116/138页
文件大小： 1048K
代理商： RCPXA273FC0416
Part 2: Flash Device Operations
Flash Programming Operations
Intel PXA27x Processor Family Memory Subsystem
79
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data
programming to the array. For Buffered EFP, the count value for buffer loading is always the
maximum buffer size of 32-words. During the buffer-loading sequence, data is stored to sequential
buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory
array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer
locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an address outside of
the current block's range during a buffer-fill sequence causes the algorithm to exit immediately.
Any data previously loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm
will be aborted and the program fail (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the flash memory
array; programming continues from where the previous buffer sequence ended. The host
programming system must poll SR.0 to determine when the buffer program sequence completes.
SR.0 cleared indicates that all buffer data has been transferred to the flash array; SR.0 set indicates
that the buffer is not available yet for the next fill cycle. The host system may check full status for
errors at any time, but it is only necessary on a block basis after Buffered EFP exit. After the buffer
fill cycle, no write cycles should be issued to the flash until SR.0 = 0 and the flash is ready for the
next buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program is
proceeding.
The host programming system continues the Buffered EFP algorithm by providing the next group
of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the
block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block address;
data supplied must be 0xFFFF. Upon Program/Verify phase completion, the flash enters the
Buffered EFP Exit phase.
11.3.4
Flash Buffered EFP Exit Phase
When SR.7 is set, the flash has returned to normal operating conditions. A full status check should
be performed on the partition being programmed at this time to ensure the entire block
programmed successfully. When exiting the Buffered EFP algorithm with a block address change,
the read mode of both the programmed and the addressed partition will not change. After Buffered
EFP exit, any valid command can be issued to the flash.
11.4
Flash Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation.
This allows data to be accessed from memory locations other than the one being programmed. The
Program Suspend command can be issued to any flash address; the corresponding partition is not
affected. A program operation can be suspended to perform reads only. Additionally, a program
operation that is running during an erase suspend can be suspended to perform a read operation.
See Figure 53, “Flash Program Suspend/Resume Flowchart” on page 114.
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RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
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