参数资料
型号: RCPXA273FC0416
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 416 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 132/138页
文件大小: 1048K
代理商: RCPXA273FC0416
Part 2: Flash Device Operations
Special Flash Read States
Intel PXA27x Processor Family Memory Subsystem
93
Special Flash Read States
15
The following sections describe non-array read states. Non-array reads can be performed in
asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous
single-word mode. When non-array reads are performed in asynchronous page mode only the first
data is valid and all subsequent data are undefined. When a non-array read operation occurs as
synchronous burst mode, the same word of data requested will be output on successive clock edges
until the burst length requirements are satisfied.
Each partition can be in one of its read states independent of other partitions’ modes. See
15.1
Flash Read Status Register
The status of any partition is determined by reading the Status Register from the address of that
particular partition. To read the Status Register, issue the Read Status Register command within the
desired partition’s address range. Status Register information is available at the partition address to
which the Read Status Register, Word Program, or Block Erase command was issued. Status
Register data is automatically made available following a Word Program, Block Erase, or Block
Lock command sequence. Reads from a partition after any of these command sequences outputs
that partition’s status until another valid command is written to that partition (e.g. Read Array
command).
The Status Register is read using single asynchronous-mode or synchronous burst mode reads.
Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous
mode the falling edge of OE#, or F-CE# (whichever occurs first) updates and latches the Status
Register contents. However, reading the Status Register in synchronous burst mode, F-CE# or
ADV# must be toggled to update status data. The Status Register read operations do not affect the
read state of the other partitions.
The flash Write Status bit (SR.7) provides overall status of the flash. The Partition Status bit (SR.0)
indicates whether the addressed partition or some other partition is actively programming or
erasing. Status register bits SR[6:1] present status and error information about the program, erase,
suspend, F-VPP, and block-locked operations.
相关PDF资料
PDF描述
RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
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