参数资料
型号: RCPXA273FC0416
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 416 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 115/138页
文件大小: 1048K
代理商: RCPXA273FC0416
Part 2: Flash Device Operations
Flash Programming Operations
78
Intel PXA27x Processor Family Memory Subsystem
11.3.1
Flash Buffered EFP Requirements and Considerations
Buffered EFP requirements:
Case temperature: TC = 25 °C, ±5 °C
F-VCC within specified operating range.
F-VPP driven to VPPH.
Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.
The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired.
WA0 must align with the start of an array buffer boundary1.
Buffered EFP considerations:
For optimum performance, cycling must be limited below 100 erase cycles per block2.
Buffered EFP programs one block at a time; all buffer data must fall within a single block3.
Buffered EFP cannot be suspended.
Programming to the flash memory array can occur only when the buffer is full4.
Read operation while performing Buffered EFP is not supported.
Notes:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
2.
Some degradation in performance may occur if this limit is exceeded, but the flash will continue to work
properly.
3.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
Flash Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, SR.7 (Ready) is cleared,
indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking
SR.7 is required to allow the WSM enough time to perform all of its setups and checks (Block-
Lock status, F-VPP level, etc.). If an error is detected, SR.4 is set and Buffered EFP operation
terminates. If the block was found to be locked, SR.1 is also set. SR.3 is set if the error occurred
due to an incorrect F-VPP level.
Note:
Reading from the flash after the Buffered EFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to be loaded into the buffer.
11.3.3
Flash Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7 cleared indicates
the flash is busy and the Buffered EFP program/verify phase is activated. SR.0 indicates the write
buffer is available.
相关PDF资料
PDF描述
RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
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