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参数资料
| 型号： | RD-19240FG-200T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MQFP-52 |
| 文件页数： | 13/19页 |
| 文件大小： | 432K |
| 代理商： | RD-19240FG-200T |
3
Data Device Corporation
www.ddc-web.com
RD-19240
F-0209-0
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation & 10% harmonic distortion.
PARAMETER
VALUE
UNIT
RESOLUTION
10, 12, or 14 (note 1)
Bits
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
±Sig/Ref Phase Shift (permissible)
(+ RH, - RL)
Differential
10 max
±5 max
±25 continuous 100 transient (note 11)
DC, 1k to 10k
10M min || 20 pf
45 max
Vpp
Vp
V
Hz
Ohm
deg
SIGNAL INPUT
Type
Voltage: operating
overload
Input Impedance
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous (note 11)
10M min || 10 pF
Vrms
V
Ohm
DIGITAL INPUT/OUTPUT (NOTE 6)
Logic Type
Inputs
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14 (EL)
Resolution and Mode Control (D1 & D0)
(see notes 1 and 8)
ZIP_EN
CMOS Compatible Inputs
SHIFT
UP/DN
A QUAD B
Outputs
Parallel Data (1-14) (note 12)
Converter Busy (CB)
TTL/CMOS compatible
Logic 0 = 0.8 V max., Logic 1 = 2.0 V min.
Loading=10 A max P.U. current source to +5 V || 5 pF max., CMOS transient protected
Logic 0 inhibits; Data stable within 150 ns
Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
Logic 1 = High Impedance, Data High Z within 100 ns (note 7)
Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
Logic 1 = High Impedance, Data High Z within 100 ns (note 7)
Mode
D1
D0
Resolution
Resolver
0
10 bits
“
0
1
12 bits
“
1
0
14 bits
LVDT
-5 V
0
8 bits
“
0
-5 V
10 bits
“
1
-5 V
12 bits
Logic 0 enables ZIP, Logic 1 enables CB
Logic 0 = 1.5 V max., Logic 1 = 3.5 V min., negative voltage = -3.5 V min.
Logic 1 selects VEL1 components, Logic 0 selects VEL2 components
Logic 0, Gain of pre-charged components will be 4
Logic 1, Gain of pre-charged components will be 1/4
Logic 0 enables encoder emulation, falling edge latches encoder resolution
10, 12, or 14 parallel lines; natural binary angle positive logic
0.25 to 0.75 s positive pulse leading edge initiates counter update
FREQUENCY RANGE
Accuracy
14-bit resolution
12-bit resolution
10-bit resolution
Repeatability due to hysteresis
Differential Linearity
14-bit resolution
12-bit resolution
10-bit resolution
Hz
Minutes
LSB
8 +1 LSB
16 +1 LSB
42 +1 LSB
± 1
< ± 3
< ± 2
8 +1 LSB
16 +1 LSB
42 +1 LSB
± 1
< ± 1
10 +1 LSB
16 +1 LSB
42 +1 LSB
± 1
< ± 2
< ± 1
TABLE 1. RD-19240 SPECIFICATIONS
DC
1k to 5k
5k to 10k
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