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参数资料
| 型号： | RD-19240FG-200T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MQFP-52 |
| 文件页数： | 18/19页 |
| 文件大小： | 432K |
| 代理商： | RD-19240FG-200T |
8
Data Device Corporation
www.ddc-web.com
RD-19240
F-02/09-0
BENEFIT OF SWITCHING RESOLUTION
ON THE FLY
Switching resolution on the fly can be used in applications that require
high resolution for accurate position control, and tracking rates or set-
tling times that are faster than the high resolution mode will allow.
The RD-19240 can track four times faster for each step down in
resolution (i.e., a step from 14 bits to 12 bits). The velocity output
will be scaled down by a factor of four with each step down in res-
olution. For example, if the velocity output is scaled such that 4
Volts = 10 RPS in 14 bit resolution, then the same converter will
output 1 Volt for 10 RPS in 12 bit resolution. To avoid glitches in
the velocity output, the second set of bandwidth components can
be pre-charged to the expected voltage, and switched in using
the SHIFT input at the same time the resolution is changed. This
will allow for a smooth velocity transition, resulting in reduced
errors and minimal settling time after the change.
FIGURE 7 shows the way the converter behaves during a
change in resolution while tracking at a constant velocity. The first
illustration shows the benefits of switching in pre-charged com-
ponents while changing resolution. The second illustration
shows the result without the benefits of switching-on-the-fly.
The signals that have been recorded are:
1) VEL: velocity output pin on the RD-19240
2) ERROR: this is the analog representation of the error between
the input and the output of the RD-19240
3) D0: an input resolution control line to the RD-19240
4) BIT: built-in-test output pin of the RD-19240
When this system uses the switch resolution on the fly imple-
mentation, the velocity signal immediately assumes the pre-
charged level of the second set of components, resulting in small
errors and reduced settling times. Notice that the BIT output,
in FIGURE 7, does not indicate a fault condition.
When this system type does not use the switch resolution on the
fly implementation, large errors and increased settling times
result. The errors exceed 100 LSBs causing the BIT to flag for a
fault condition.
SWITCH ON THE FLY IMPLEMENTATION
The following steps detail switching resolution on the fly.
Note: Refer to www.ddc-web.com for a detailed application
note (AN/MFT3) on switching resolutions on the fly.
1) The SHIFT pin should be controlled synchronously with the
change in resolution. When shift is logic high, the VEL1 com-
ponents will be selected. When shift is logic 0, the VEL2 com-
ponents will be selected.
2) The second set of BW components (CBW2, RB2, CBW2/10)
should typically be of the same value as the first set (CBW1,
RB1, CBW1/10) and should be installed on VEL2 and VEL SJ2.
Note: Each set of bandwidth components must be chosen to
insure that the tracking rate to BW ratio (listed in TABLE 2)
is not exceeded for the resolution in which it will be used.
FIGURE 7. BENEFIT OF SWITCHING
RESOLUTION ON THE FLY
Without Switch Resolution on the Fly Implemented
With Switch Resolution on the Fly Implemented
VEL
0V
-5V
ERROR 0
D0
0V
5V
BIT
0V
5V
ERROR = 13.6 LSBs per box
Note: Depending on bandwidth, step error may be greater.
VEL
0V
-5V
ERROR 0
D0
0V
5V
BIT
0V
5V
ERROR = 1500 LSBs per box
Note: Depending on bandwidth, step error may be greater.
Also, less velocity / movement will lessen the error
glitch shown in the graph. The graph shows a worst
case condition based upon one bandwidth and track-
ing rate set-up. Worst case is when the overshoot on
the velocity hits the saturation point as per the graph.
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