6
Data Device Corporation
www.ddc-web.com
RD-19240
F-02/09-0
2) The converter has two internal ground planes, which reduce
noise to the analog input due to digital ground currents. The
resolver inputs and velocity output are referenced to AGND.
The digital outputs and inputs are referenced to GND. The
AGND and GND pins must be tied together as close to the
converter package as possible. Not shorting these pins
together as close to the converter package as possible may
cause unstable converter results.
3) To setup the bandwidth and velocity scaling for optimized
application dynamics, use DDC’s “External Components
Calculation Software” available at www.ddc-web.com.
4) Selecting a fBW that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationships to insure
against spin-around are shown in TABLE 2.
5) To ensure low noise performance when using the ±5 V power
supplies, it is recommended that a 0.1F or larger capacitor be
connected from each supply to ground near the converter pack-
age. When using a +5 V and -5 V supply to power the convert-
er, pins VSSP, NCAP, PCAP, and VDDP must be no connection.
Connect both VDD pins to +5 VDC, and both VSS pins to -5 VDC.
6) When using the built-in -5 V inverter (connect as shown in
FIGURE 5) the current drain from the +5 V supply doubles. No
external -5 V supply is needed. The power supply 47f caps
shown may be substituted with 10f caps if the P/S lines are
clean (min noise). Connect both VDD pins, along with the VDDP
pin, to +5VDC. Connect both VSS pins to VSSP.
When using the built-in -5 V inverter, the maximum tracking rate
should be scaled for a velocity output of 3.5 V max. Refer to the
following equation to determine the tracking rate required by
DDC’s “External Components Calculation Software” used in
Step 3:
FIGURE 5. -5V BUILT-IN INVERTER
TABLE 3. MAX TRACKING RATE (MIN) IN RPS
RC & RSET*
(
Ω
Ω)
RS & RCLK*
(
Ω
Ω)
RESOLUTION
10
12
14
30k** or open
30k
1152
288
72
23k
20k
1200
432
108
23k
15k
1200
576
108
* RC “Rcurrent” = RSET
RS “Rsample” = RCLK
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
***
10
15k
20k
23k
10
30k
23k
7
10
30k
30k** or open
14
12
10
RESOLUTION
RS & RCLK*
(
Ω
Ω)
RC & RSET*
(
Ω
Ω)
TABLE 4. CARRIER FREQUENCY (MAX) IN KHZ
* RC “Rcurrent” = RSET
RS “Rsample” = RCLK
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
*** Not recommended.
+
10
F/10V
VDD
PCAP
+5V
NCAP
GND
AGND
VSSP
RD-19240
47
F/10V
VDD
VDDP
VSS*
VSS
+
47
F
TABLE 2. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
10
0.50
12
0.25
14
Note: When using the highest BW and Tracking Rates, use of the -5 V inverter is
not recommended.
HIGHER TRACKING RATES AND
CARRIER FREQUENCIES
Maximum tracking rate is limited by the velocity voltage saturation
(nominally 4 V) and the maximum internal clock rate (nominally
1,333,333 Hz for R CLK = 30k). To achieve higher tracking rates, a
higher internal counting rate must be programmed by setting RCLK
to a value less than 30k. See TABLE 3 for the appropriate values.
Select freq/resolution from TABLE 4 then reference TABLE 3 for
max tracking rate. The Rv resistor and an internal 50pF capaci-
tor are configured as an integrating circuit that resets to zero
after a count occurs in either direction. This circuit acts as a VCO
with velocity as its input and CB as its output. The Rv resistor and
an internal 50pF capacitor determine the maximum rate of the
VCO. Rv must be chosen such that the maximum rate of the
VCO is less than the maximum internal clock rate. Choose the
tracking rate in accordance with TABLE 3 to insure this relation-
ship. The rates shown in TABLE 3 are based on ~90% of the
nominal internal clock rate.
The relationship between the velocity voltage and the VCO rate
is given by:
Velocity Voltage
VCO Frequency
1
(Rv x 50 pF x 1.25)
=
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)