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| 型号： | RDK-242 |
| 厂商： | Power Integrations |
| 文件页数： | 16/40页 |
| 文件大小： | 0K |
| 描述： | KIT REF DESIGN VG TOPSWITCH-JX |
| 标准包装： | 1 |
| 系列： | TOPSwitch®-JX |
| 主要目的： | AC/DC，主面和辅面 |
| 输出及类型： | 1，隔离 |
| 功率 - 输出： | 30W |
| 输出电压： | 12V |
| 电流 - 输出： | 2.5A |
| 输入电压： | 85 ~ 264VAC |
| 稳压器拓扑结构： | 回扫 |
| 频率 - 开关： | 132kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | TOP266VG |
| 其它名称： | 596-1312 |
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TOP264-271
Higher current rating, low V F Schottky rectifier diode selected
TOPSwitch-JX MOSFET. This arrangement was selected over
a standard RCD clamp to improve light load efficiency and no-load
input power.
In a standard RCD clamp C4 would be discharged by a parallel
resistor rather than a resistor and series Zener. In an RCD clamp
the resistor value is selected to limit the peak drain voltage
under full load and overload conditions. However under light or
no-load conditions this resistor value now causes the capacitor
voltage to discharge significantly as both the leakage inductance
energy and switching frequency are lower. As the capacitor has
to be recharged to above the reflected output voltage each
switching cycle the lower capacitor voltage represents wasted
energy. It has the effect of making the clamp dissipation
appear as a significant load just as if it were connected to the
output of the power supply.
The RZCD arrangement solves this problem by preventing the
voltage across the capacitor discharging below a minimum
value (defined by the voltage rating of VR2) and therefore
minimizing clamp dissipation under light and no-load conditions.
Resistors R6 and R28 provide damping of high frequency
ringing to reduce EMI. Due to the resistance in series with VR2,
limiting the peak current, standard power Zeners vs a TVS type
may be used for lower cost (although a TVS type was selected
due to availability of a SMD version). Diode D2 was selected to
have an 800 V vs the typical 600 V rating due to its longer
reverse recovery time of 500 ns. This allows some recovery of
the clamp energy during the reverse recovery time of the diode
improving efficiency. Multiple resistors were used in parallel to
share dissipation as SMD components were used.
Feedback Configuration
? A Darlington connection formed together with optocoupler
transistor to reduce secondary-side feedback current and
therefore no-load input power
? Low voltage, low current voltage reference IC used on
secondary-side to reduce secondary-side feedback current
and therefore no-load input power
? Bias winding voltage tuned to ~9 V at no-load, high-line to
reduce no-load input power
Typically the feedback current into the CONTROL pin at high
line is ~3 mA. This current is both sourced from the bias
winding (voltage across C10) and directly from the output. Both
of these represent a load on the output of the power supply.
16
Rev. E 08/12
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C10
was adjusted to give a minimum voltage across C10 of ~9 V.
This is the minimum required to keep the optocoupler biased.
To minimize the dissipation of the secondary-side feedback
circuit Q2 was added to form a Darlington connection with U3B.
This reduced the feedback current on the secondary to ~1 mA.
The increased loop gain (due to the h FE of the transistor) was
compensated by increasing the value of R16 and the addition of
R25. A standard 2.5 V TL431 voltage reference was replaced
with the 1.24 V LMV431 to reduce the supply current requirement
from 1 mA to 100 m A.
Output Rectifier Choice
?
for output rectifier
A dual 15 A, 100 V Schottky rectifier diode with a V F of 0.455 V
at 5 A was selected for D5. This is a higher current rating than
required to reduce resistive and forward voltage losses to improve
both full load and average efficiency. The use of a 100 V Schottky
was possible due to the high transformer primary to secondary
turns ratio (V OR = 110 V) which was in turn possible due to the
high-voltage rating of the TOPSwitch-JX internal MOSFET.
Increased Output Overvoltage Shutdown Sensitivity
? Transistor Q1 and VR1 added to improve the output over-
voltage shutdown sensitivity
During an open loop condition the output and therefore bias
winding voltage will rise. When this exceeds the voltage of VR1
plus a V BE voltage drop Q1 turns on and current is fed into the
V pin. The addition of Q1 ensures that the current into the V pin
is sufficient to exceed the latching shutdown threshold even
when the output is fully loaded while the supply is operating at
low-line as under this condition the output voltage overshoot is
relatively small
Output overload power limitation is provided via the current limit
programming feature of the X pin and R7, R8 and R9. Resistors
R8 and R9 reduce the device current limit as a function of
increasing line voltage to provide a roughly flat overload power
characteristic, below the 100 VA limited power source (LPS)
requirement. In order to still meet this under a single fault
condition (such as open circuit of R8) the rise in the bias voltage
that occurs during an overload condition is also used to trigger
a latching shutdown.
www.powerint.com
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