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| 型号： | RDK-242 |
| 厂商： | Power Integrations |
| 文件页数： | 5/40页 |
| 文件大小： | 0K |
| 描述： | KIT REF DESIGN VG TOPSWITCH-JX |
| 标准包装： | 1 |
| 系列： | TOPSwitch®-JX |
| 主要目的： | AC/DC，主面和辅面 |
| 输出及类型： | 1，隔离 |
| 功率 - 输出： | 30W |
| 输出电压： | 12V |
| 电流 - 输出： | 2.5A |
| 输入电压： | 85 ~ 264VAC |
| 稳压器拓扑结构： | 回扫 |
| 频率 - 开关： | 132kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | TOP266VG |
| 其它名称： | 596-1312 |
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TOP264-271
hysteretic output overvoltage protection (OVP). The pin can
also be used as a remote ON/OFF using the I UV threshold.
The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce
the current limit externally to a value close to the operating peak
current, by connecting the pin to SOURCE through a resistor.
This pin can also be used as a remote ON/OFF input.
The FREQUENCY (F) pin sets the switching frequency in the full
frequency PWM mode to the default value of 132 kHz when
connected to SOURCE pin. A half frequency option of 66 kHz
can be chosen by connecting this pin to the CONTROL pin
instead. Leaving this pin open is not recommended.
CONTROL (C) Pin Operation
The CONTROL pin is a low impedance node that is capable of
receiving a combined supply and feedback current. During
normal operation, a shunt regulator is used to separate the
feedback signal from the supply current. CONTROL pin voltage
V C is the supply voltage for the control circuitry including the
MOSFET gate driver. An external bypass capacitor closely
connected between the CONTROL and SOURCE pins is
required to supply the instantaneous gate drive current. The
total amount of capacitance connected to this pin also sets the
auto-restart timing as well as control loop compensation.
When rectified DC high-voltage is applied to the DRAIN pin
during start-up, the MOSFET is initially off, and the CONTROL
pin capacitor is charged through a switched high-voltage
current source connected internally between the DRAIN and
CONTROL pins. When the CONTROL pin voltage V C reaches
approximately 5.8 V, the control circuitry is activated and the
soft-start begins. The soft-start circuit gradually increases the
drain peak current and switching frequency from a low starting
value to the maximum drain peak current at the full frequency
over approximately 17 ms. If no external feedback/supply
current is fed into the CONTROL pin by the end of the soft-start,
the high-voltage current source is turned off and the CONTROL
pin will start discharging in response to the supply current
drawn by the control circuitry. If the power supply is designed
properly, and no fault condition such as open loop or shorted
output exists, the feedback loop will close, providing external
CONTROL pin current, before the CONTROL pin voltage has
had a chance to discharge to the lower threshold voltage of
approximately 4.8 V (internal supply undervoltage lockout
threshold). When the externally fed current charges the CONTROL
pin to the shunt regulator voltage of 5.8 V, current in excess of
the consumption of the chip is shunted to SOURCE through an
NMOS current mirror as shown in Figure 3. The output current
of that NMOS current mirror controls the duty cycle of the
power MOSFET to provide closed loop regulation. The shunt
regulator has a finite low output impedance Z C that sets the gain
of the error amplifier when used in a primary feedback
configuration. The dynamic impedance Z C of the CONTROL pin
together with the external CONTROL pin capacitance sets the
dominant pole for the control loop.
When a fault condition such as an open loop or shorted output
prevents the flow of an external current into the CONTROL pin,
the capacitor on the CONTROL pin discharges towards 4.8 V.
At 4.8 V, auto-restart is activated, which turns the output
www.powerint.com
MOSFET off and puts the control circuitry in a low current
standby mode. The high-voltage current source turns on and
charges the external capacitance again. A hysteretic internal
supply undervoltage comparator keeps V C within a window of
typically 4.8 V to 5.8 V by turning the high-voltage current
source on and off as shown in Figure 8. The auto-restart circuit
has a divide-by-sixteen counter, which prevents the output
MOSFET from turning on again until sixteen discharge/charge
cycles have elapsed. This is accomplished by enabling the
output MOSFET only when the divide-by-sixteen counter
reaches the full count (S15). The counter effectively limits
TOP264-271 power dissipation by reducing the auto-restart
duty cycle to typically 2%. Auto-restart mode continues until
output voltage regulation is again achieved through closure of
the feedback loop.
Oscillator and Switching Frequency
The internal oscillator linearly charges and discharges an
internal capacitance between two voltage levels to create a
triangular waveform for the timing of the pulse width modulator.
This oscillator sets the pulse width modulator/current limit latch
at the beginning of each cycle.
The nominal full switching frequency of 132 kHz was chosen to
minimize transformer size while keeping the fundamental EMI
frequency below 150 kHz. The FREQUENCY pin, when shorted
to the CONTROL pin, lowers the full switching frequency to
66 kHz (half frequency), which may be preferable in some cases
such as noise sensitive video applications or a high efficiency
standby mode. Otherwise, the FREQUENCY pin should be
connected to the SOURCE pin for the default 132 kHz.
To further reduce the EMI level, the switching frequency in the
full frequency PWM mode is jittered (frequency modulated) by
approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for
132 kHz operation at a 250 Hz (typical) rate as shown in Figure 7.
The jitter is turned off gradually as the system is entering the
variable frequency mode with a fixed peak drain current.
Pulse Width Modulator
The pulse width modulator implements multi-mode control by
driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 6).
The feedback error signal, in the form of the excess current, is
filtered by an RC network with a typical corner frequency of
7 kHz to reduce the effect of switching noise in the chip supply
current generated by the MOSFET gate driver.
To optimize power supply efficiency, four different control
modes are implemented. At maximum load, the modulator
operates in full frequency PWM mode; as load decreases, the
modulator automatically transitions, first to variable frequency
PWM mode, then to low frequency PWM mode. At light load,
the control operation switches from PWM control to multi-cycle-
modulation control, and the modulator operates in multi-cycle-
modulation mode. Although different modes operate differently
to make transitions between modes smooth, the simple
relationship between duty cycle and excess CONTROL pin
current shown in Figure 6 is maintained through all three PWM
5
Rev. E 08/12
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