Pin Listing and Signal Definitions
Intel Xeon Processor MP with up to 2MB L3 Cache
9-1
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Pin Name
Pin No.
Signal
Buffer Type
Direction
A3#
A22
Source Sync
Input/Output
A4#
A20
Source Sync
Input/Output
A5#
B18
Source Sync
Input/Output
A6#
C18
Source Sync
Input/Output
A7#
A19
Source Sync
Input/Output
A8#
C17
Source Sync
Input/Output
A9#
D17
Source Sync
Input/Output
A10#
A13
Source Sync
Input/Output
A11#
B16
Source Sync
Input/Output
A12#
B14
Source Sync
Input/Output
A13#
B13
Source Sync
Input/Output
A14#
A12
Source Sync
Input/Output
A15#
C15
Source Sync
Input/Output
A16#
C14
Source Sync
Input/Output
A17#
D16
Source Sync
Input/Output
A18#
D15
Source Sync
Input/Output
A19#
F15
Source Sync
Input/Output
A20#
A10
Source Sync
Input/Output
A21#
B10
Source Sync
Input/Output
A22#
B11
Source Sync
Input/Output
A23#
C12
Source Sync
Input/Output
A24#
E14
Source Sync
Input/Output
A25#
D13
Source Sync
Input/Output
A26#
A9
Source Sync
Input/Output
A27#
B8
Source Sync
Input/Output
A28#
E13
Source Sync
Input/Output
A29#
D12
Source Sync
Input/Output
A30#
C11
Source Sync
Input/Output
A31#
B7
Source Sync
Input/Output
A32#
A6
Source Sync
Input/Output
A33#
A7
Source Sync
Input/Output
A34#
C9
Source Sync
Input/Output
A35#
C8
Source Sync
Input/Output
A20M#
F27
Async GTL+
Input
ADS#
D19
Common Clk
Input/Output
ADSTB0#
F17
Source Sync
Input/Output
ADSTB1#
F14
Source Sync
Input/Output
AP0#
E10
Common Clk
Input/Output
AP1#
D9
Common Clk
Input/Output
BCLK0
Y4
Sys Bus Clk
Input
BCLK1
W5
Sys Bus Clk
Input
BINIT#
F11
Common Clk
Input/Output
BNR#
F20
Common Clk
Input/Output
BPM0#
F6
Common Clk
Input/Output
BPM1#
F8
Common Clk
Input/Output
BPM2#
E7
Common Clk
Input/Output
BPM3#
F5
Common Clk
Input/Output
BPM4#
E8
Common Clk
Input/Output
BPM5#
E4
Common Clk
Input/Output
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Pin Name
Pin No.
Signal
Buffer Type
Direction
Pin Listing and Signal Definitions
9
9.1
Intel Xeon Processor MP on the 0.13 Micron
Process Processor Pin Assignments
Section 2.8 contains the system bus signal groups in
Table 5 for the Intel Xeon processor MP on the
0.13 micron process processor. This section provides a sorted pin list in
Table 50 and
Table 51 for
INT-mPGA package.
Table 50 is a listing of all processor pins ordered alphabetically by pin name.
Table 51 is a listing of all processor pins ordered by pin number.