参数资料
型号: RN80532KC0411M
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 2000 MHz, MICROPROCESSOR, CPGA603
封装: Interposer, Micro, PGA-603
文件页数: 61/132页
文件大小: 2316K
代理商: RN80532KC0411M
Electrical Specifications
2-20
Intel Xeon Processor MP with up to 2MB L3 Cache
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (VCROSS). All Asynchronous GTL+ signal timings are referenced at GTLREF. PWRGOOD is
referenced to the BCLK0 rising edge at 0.5*VCC.
3. These signals may be driven asynchronously.
4. Refer to Section 6.2 for additional timing requirements for entering and leaving low power states.
5. Refer to the PWRGOOD signal definition in Section 9.2 for more detail information on behavior of the signal.
6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion of PROCHOT# for the processor to complete current instruction execution
.
NOTES:
1. Before the de-assertion of RESET#
2. After the clock that de-asserts RESET#
.
Table 18. Miscellaneous Signals AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T35: Async GTL+ input pulse width
2
N/A
BCLKs
1, 2, 3, 4
T36: PWRGOOD to RESET# de-assertion time
1
10
ms
1, 2, 3, 4
T37: PWRGOOD inactive pulse width
10
N/A
BCLKs
1, 2, 3, 4, 5
T38: PROCHOT# pulse width
500
s
1, 2, 3, 4, 6
T39: THERMTRIP# to Vcc Removal
0.5
s
T40: FERR# Valid Delay from STPCLK#
deassertion
05
BCLKs
Table 19. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Setup Time
4BCLKs
1
T46: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
220
BCLKs
2
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