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参数资料
| 型号： | RN80532KC0411M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | Interposer, Micro, PGA-603 |
| 文件页数： | 41/132页 |
| 文件大小： | 2316K |
| 代理商： | RN80532KC0411M |
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Electrical Specifications
2-2
Intel Xeon Processor MP with up to 2MB L3 Cache
minimum values if bulk decoupling is not adequate. Larger bulk storage (C
BULK), such as
electrolytic capacitors, supply current during longer lasting changes in current demand by the
component, such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the baseboard
design to ensure that the voltage provided to the processor remains within the specifications listed
in Table 7. Failure to do so can result in timing violations or reduced lifetime of the component. For
further information and guidelines, refer to the appropriate platform design guidelines.
2.3.1
V
CC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must assure a low interconnect resistance from the regulator (or VRM
pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module
(VRM) to meet, in part, the need to handle large current swings. The remaining decoupling is
provided on the baseboard. The power delivery path must be capable of delivering enough current
while maintaining the required tolerances (defined in Table 7). For further information regarding
power delivery, decoupling, and layout guidelines, refer to the appropriate platform design
guidelines.
2.3.2
System Bus AGTL+ Decoupling
The Intel Xeon processor MP on the 0.13 micron process integrates signal termination on the die as
well as part of the required high frequency decoupling capacitance on the processor package.
However, additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the system bus. Bulk decoupling must also be provided by the
baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate
platform design guidelines.
2.4
System Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Intel Xeon processor MP on the 0.13 micron
process processor core frequency is a multiple of the BCLK[1:0] frequency. The Intel Xeon
processor MP on the 0.13 micron process processor bus ratio multiplier will be set during
manufacturing. The default setting will equal the maximum speed for the processor. It will be
possible to override this setting using software. This will permit operation at speeds lower than the
processor’s tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The
processor core frequency is configured during Reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate ratio can be set with software using
MSR_EBC_FREQ_GOAL to produce a lower operating speed. For details of operation at core
frequencies lower than the maximum rated processor speed.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications must be met while also meeting signal integrity requirements as outlined in
Section 3. The Intel Xeon processor MP on the 0.13 micron process processor utilizes a differential
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相关代理商/技术参数 |
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| RN80532KC041512S L6W6 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
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