参数资料
型号: RPIXP2800BC
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 650 MHz, RISC PROCESSOR, PBGA1356
封装: 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356
文件页数: 35/130页
文件大小: 1782K
代理商: RPIXP2800BC
Intel IXP2800 and IXP2850 Network Processors
Functional Units
Datasheet
13
2.6.2
SRAM Controller Configurations
Each channel has enough address pins (24) to support up to 64 Mbyte of SRAM. The SRAM
controllers can directly generate multiple port enables (up to four pairs) to allow for depth
expansion. Two pairs of pins are dedicated for port enables. Smaller RAMs use fewer address
signals than the number provided to accommodate the largest RAMs, so some address pins (23:20)
are configurable as either address or port-enable, based on the CSR setting as shown in Table 1.
Note:
All of the SRAMs on a given channel must be the same size.
Figure 5. Clocking Scheme for a QDR Interface Driving Four SRAMs
A9234-03
Clam-shelled SRAMS
Package Balls
Termination
Intel
IXP2800
Network
Processor
C0IN/C0IN#
K0/K0#
K/K#
C/C#
C0/C0#
K1/K1#
C1/C1#
C0/C0#
C1/C1#
C1IN/C1IN#
Termination
Table 1.
SRAM Controller Configurations
SRAM
Configuration
SRAM Size
Addresses Needed
to Index SRAM
Addresses Used
as Port Enables
Total Number of
Port Select Pairs
Available
512K x 18
1 Mbyte
17:0
23:22, 21:20
4
1M x 18
2 Mbyte
18:0
23:22, 21:20
4
2M x 18
4 Mbyte
19:0
23:22, 21:20
4
4M x 18
8 Mbyte
20:0
23:22
3
8M x 18
16 Mbyte
21:0
23:22
3
16M x 18
32 Mbyte
22:0
None
2
32M x 18
64 Mbyte
23:0
None
1
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