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参数资料
| 型号： | RS5C372A-E2 |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 0.65 MM PITCH, SSOP-8 |
| 文件页数： | 39/59页 |
| 文件大小： | 442K |
| 代理商： | RS5C372A-E2 |
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RS5C372A/B
40
3. Oscillator Halt Sensing
Oscillation halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to 0 by writ-
ing data to the control register 2. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This function
can be applied to judge clock data validity. When the XSTP bit is 1, XSL, F6 to F0, CT2, CT1, CT0, AALE, BALE, SL2,
SL1, CLEN and TEST bits are reset to 0.
Considerations in Use of XSTP Bit
Ensure error-free oscillation halt sensing by preventing the following events:
1) Instantaneous disconnection of VDD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC.
*1) The XSTP bit is set to 1 upon power-on from 0V.
Note that any instantaneous power disconnection may cause operation failure.
*2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
4. INTRA Output and INTRB Output Pins (RS5C372A), INTR Output Pin (RS5C372B)
4.1 INTRA Output and INTRB Output Pins (RS5C372A)
The following three output wave forms can be output from the INTRA or the INTRB pin.
1) Alarm interrupt
When a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar counter (such
as day-of-the-week, hour or minute) interrupt to the CPU are requested with the output pin being on (“L”). Alarm
interrupt consists of Alarm_A and Alarm_B, both have equivalent functions.
2) Periodic interrupt
Outputs an output wave form selected by setting the periodic interrupt frequency select bit. Wave forms include
pulse mode and level mode.
3) 32-kHz clock output
Clock pulses generated in the oscillation circuit are output as they are.
4.1-1 Control of the INTRA, INTRB Output (flag bit, enable bit, interrupt output select bit) (RS5C372A)
Of the three output wave forms listed above, interrupt output conditions may be set by setting the flag bit that moni-
tors output state on the register, the enable bit that enables an output wave form and the output select bit that
selects either INTRA or INTRB to be output a wave form to.
Interrupt output select bit (SL2, SL1)
Flag bit
Enable bit
(D5, D4 at Eh)
(0,0)
(0,1)
(1,0)
(1,1)
Alarm_A
AAFG (D1 at Fh)
AALE (D7 at Eh)
INTRA
Alarm_B
BAFG (D0 at Fh)
BALE (D6 at Eh)
INTRA
INTRB
INTRA
INTRB
Periodic interrupt
CTFG (D2 at Fh)
Disabled at CT2=CT1=CT0=0
INTRA
INTRB
(D2 to D0 at Eh)
32-kHz clock output
No
CLEN (D3 at Fh)
INTRB
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RS5C372B | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C372B-E1 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C372B-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C373A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RS5C4FC | 制造商:Dialight 功能描述: |
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