
RS5C372A/B
43
4.3 Periodic (Clock) Interrupt
The INTRA or INTRB pin (INTR for the RS5C372B) output, the periodic interrupt cycle select bits (CT2, CT1, CT0) and
the interrupt output select bits (SL2, SL1) can be used to interrupt the CPU in a certain cycle. The periodic interrupt
cycle select bits can be used to select either one of two interrupt output modes: the pulse mode and the level mode.
Interrupt Cycle Selection
CT2
CT1
CT0
Description
Wave From Mode
Cycle and Falling Timing
0
—
OFF (Default)
0
1
—
Fixed at “L”
0
1
0
Pulse mode
2Hz (Duty50%)
0
1
Pulse mode
1Hz (Duty50%)
1
0
Level mode
Every second (coincident with second count-up)
1
0
1
Level mode
Every minute (at 00 second)
1
0
Level mode
Every hour (at 00:00 on the hour)
1
Level mode
Every month (1st day, 00:00:00 a.m.)
1) Pulse mode : Outputs 2Hz, 1Hz clock pulses. For relationships with counting up of seconds see the diagram
below.
*) When 32.000kHz crystal is used,
In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternately.
Duty cycle for 1Hz clock pulses becomes 50.4% (“L” duration is 0.496s while “H” duration is 0.504s).
4.2-2 Alarm Interrupt (RS5C372B)
For setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the alarm regis-
ters being AALE (BALE) bit to 0. After that set the AALE (BALE) bit to 1, from this moment onward when such
registered alarm time coincide the value of calendar counter the INTR comes down to “L” (ON). The INTR output
can be controlled by operating to the AALE (BALE) and AAFG (BAFG) bits.
Alarm-calendar coincidence
period (1 min.)
Day-of-
the-week,
time
matched
Day-of-
the-week,
time
matched
Day-of-
the-week,
time
matched
Day-of-
the-week,
time
matched
INTR
AALE
←1
(BALE)
AALE
←1
(BALE)
AALFG
←0
(BAFG)
AALE
←0
(BALE)
AALE
←0
(BALE)
AALE
←1
(BALE)
A
A : MAX.61.1
s
(MAX. 62.5
s when 32.000kHz crystal is used.)
*) Note that AAFG (BAFG) has an output wave form of reversed logic.