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参数资料
| 型号： | RX-4571LC |
| 厂商： | EPSON TOYOCOM CORP |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO12 |
| 封装： | ROHS COMPLIANT, VSOJ-12 |
| 文件页数： | 13/33页 |
| 文件大小： | 723K |
| 代理商： | RX-4571LC |
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RX
4571 LC
Page - 17
ETM18E-04
13.1.8. Flag Register ( Reg
0E [h] )
Address [h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
E
Flag Register
TEST2
TF
AF
VLF
RSV
This is a flag register that indicates circumstantial results, such as the state of power supply, the generated state
of various interrupt events, the reliability of internal data, and the like.
1) TEST2, RSV bit
Those bits are the manufacturer's test bit.
Always leave this bit value as "0" except when testing.
Be careful to avoid writing to this bit when writing "1" to other bits in this register.
The three TEST* bits are undefined when read. Those bits should be masked after being read.
2) TF bit ( Timer Flag )
This flag bit holds the result of the detection of a fixed-cycle timer interrupt event.
If a fixed-cycle timer interrupt event is generated, this bit shifts from "0" to "1."
For details, see "13.2. Fixed-cycle Timer Interrupt Function".
3) AF bit ( Alarm Flag )
This is a flag bit that retains the result when an alarm interrupt event has been detected.
When an alarm interrupt event occurs, this bit's value changes from "0" to "1".
For details, see "13.4. Alarm Interrupt Function".
4) VLF bit ( Voltage Low Flag )
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to
"1" when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value
is retained until a "0" is written to it.
During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure
to initialize all registers before using them.
VLF
Data
Description
0
The VLF is cleared to 0, and waiting for next low voltage detection.
Write
1
It is impossible to write in 1 to VLF.
0
RTC register data are valid.
Read
1
RTC register data are invalid.
Should be initialized of all register data.
VLF is maintained till it is cleared by zero.
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| RX-4571SA | REAL TIME CLOCK, PDSO14 |
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相关代理商/技术参数 |
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| RX-4571NB | 制造商:EPSONTOYOCOM 制造商全称:Epson ToYoCom 功能描述:LOW BACKUP VOLTAGE SERIAL-INTERFACE REAL TIME CLOCK MODULE |
| RX-4571SA | 制造商:EPSONTOYOCOM 制造商全称:Epson ToYoCom 功能描述:LOW BACKUP VOLTAGE SERIAL-INTERFACE REAL TIME CLOCK MODULE |
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