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参数资料
| 型号： | RX-4571LC |
| 厂商： | EPSON TOYOCOM CORP |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO12 |
| 封装： | ROHS COMPLIANT, VSOJ-12 |
| 文件页数： | 17/33页 |
| 文件大小： | 723K |
| 代理商： | RX-4571LC |
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RX
4571 LC
Page - 21
ETM18E-04
3) TE bit ( Timer Enable )
When TE bit is "0", the default (preset) can be checked by reading this register.
TE
Data
Description
0
Stops fixed-cycle timer interrupt function.
Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-Z).
Write / Read
1
Starts fixed-cycle timer interrupt function.
The countdown that starts when the TE bit value changes from "0" to "1" always begins from the
preset value.
4) TF bit ( Timer Flag )
This is a flag bit that retains the result when a fixed-cycle timer interrupt event is detected.
If it was already cleared to zero, this value changes from "0" to "1" when an event occurs, and the new
value is retained.
TF
Data
Description
0
The TF bit is cleared to zero to prepare for the next status detection
Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-Z).
Write
1
This bit is invalid after a "1" has been written to it.
0
Fixed-cycle timer interrupt events are not detected.
Read
1
Fixed-cycle timer interrupt events are detected.
(Result is retained until this bit is cleared to zero.)
5) TIE bit ( Timer Interrupt Enable )
This bit is used to control output of interrupt signals from the /IRQ pin when a fixed-cycle timer interrupt
event has occurred.
When a "1" is written to this bit, occurrence of an interrupt event causes a low-level interrupt signal to be
output from /IRQ pin.
When a "0" is written to this bit, output from the /IRQ pin is prohibited (disabled).
TIE
Data
Description
0
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/IRQ status remains Hi-Z).
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is
canceled (/IRQ status changes from low to Hi-Z).
Even when the TIE bit value is "0" another interrupt event may change the /IRQ status to low (or
may hold /IRQ = "L").
Write / Read
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/IRQ status changes from Hi-Z to low).
13.2.3. Fixed-cycle timer start timing
Counting down of the fixed-cycle timer value starts at the falling edge of the CLK signal that occurs when the TE
value is changed from "0" to "1" (after bit 0 is transferred).
/ IRQ pin
SDA pin
SCL pin
Internal timer
Address D
TE
FSEL1 FSEL0
TSEL1 TSEL0
Operation of timer
( 1st period )
Operation of timer
( 2nd period )
相关PDF资料 |
PDF描述 |
|---|---|
| RX-4571SA | REAL TIME CLOCK, PDSO14 |
| RX-4571SA | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RX-4574SG | 0 TIMER(S), REAL TIME CLOCK, PDSO16 |
| RX-4591CF | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| RX-8025NB | 0 TIMER(S), REAL TIME CLOCK, PDSO22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RX-4571NB | 制造商:EPSONTOYOCOM 制造商全称:Epson ToYoCom 功能描述:LOW BACKUP VOLTAGE SERIAL-INTERFACE REAL TIME CLOCK MODULE |
| RX-4571SA | 制造商:EPSONTOYOCOM 制造商全称:Epson ToYoCom 功能描述:LOW BACKUP VOLTAGE SERIAL-INTERFACE REAL TIME CLOCK MODULE |
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