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参数资料
| 型号： | S1C63158B0A010R |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA |
| 文件页数： | 151/159页 |
| 文件大小： | 1200K |
| 代理商： | S1C63158B0A010R |
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S1C63808 TECHNICAL MANUAL
EPSON
83
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(2) Port selection
Because serial interface input/output terminals SINx and SOUTx are set as I/O port terminals
P10/P20 and P11/P21 at initial reset, "1" must be written to the serial interface enable register
ESIFx in order to set these terminals for serial interface use.
SCLKx and SRDYx terminals set in the clock synchronous mode are not used in the asynchronous
mode. These terminals function as I/O port terminals P12/P22 and P13/P23.
(3) Setting of transfer mode
Select the asynchronous mode by writing the data as indicated below to the two bits of the mode
selection registers SMDx0 and SMDx1.
7-bit mode: SMDx0 = "0", SMDx1 = "1"
8-bit mode: SMDx0 = "1", SMDx1 = "1"
(4) Parity bit selection
When checking and adding parity bits, write "1" into the parity enable register EPRx to set to "with
parity check". As a result of this setting, in the 7-bit asynchronous mode, it has a 7 bits data +
parity bit configuration and in the 8-bit asynchronous mode it has an 8 bits data + parity bit
configuration. In this case, parity checking for receiving and adding a party bit for transmitting is
done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or
"even" parity must be further selected in the parity mode selection register PMDx.
When "0" is written to the EPRx register to select "without parity check" in the 7-bit asynchronous
mode, data configuration is set to 7 bits data (no parity) and in the 8-bit asynchronous mode (no
parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done.
(5) Clock source selection
Select the clock source by writing data to the two bits of the clock source selection registers SCSx0
and SCSx1. (See Table 4.10.4.1.)
(6) Clock source control
When the programmable timer is selected for the clock source, set transfer rate on the programma-
ble timer side. (See "4.9 Programmable Timer".)
When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the
OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "4.3 Oscillation
Circuit".)
(7) Stop bit length selection
The stop bit length can be configured to 1 bit or 2 bits using the stop bit select register STPBx.
Table 4.10.7.1 Stop bit and parity bit settings
EPRx
1
0
1
0
STPBx
1
0
PMDx
1
0
–
1
0
–
Stop bit
2 bits
1 bit
Parity bit
Odd
Even
Non parity
Odd
Even
Non parity
Settings
(8) Serial data input/output permutation
The S1C63808 provides the data input/output permutation select register SDPx to select whether
the serial data bits are transferred from the LSB or MSB. The SDPx register should be set before
writing data to TRXDx0–TRXDx7.
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