参数资料
型号: S1C63158B0A010R
元件分类: 微控制器/微处理器
英文描述: 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA
文件页数: 21/159页
文件大小: 1200K
代理商: S1C63158B0A010R
S1C63808 TECHNICAL MANUAL
EPSON
109
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.13 SVD (Supply Voltage Detection) Circuit
4.13.1 Configuration of SVD circuit
The S1C63808 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers. Turning the SVD circuit on/off and the SVD criteria voltage setting can be done
with software. Figure 4.13.1.1 shows the configuration of the SVD circuit.
V
Detection output
Data
bus
DD
VSS
SVDON
SVDCHG
SVDS2–0
Criteria voltage
setting circuit
SVD circuit
SVDDT
Fig. 4.13.1.1 Configuration of SVD circuit
4.13.2 SVD operation
The SVD circuit compares the criteria voltage set by software and the supply voltage (VDD terminal–VSS
terminal) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be
determined by means of software whether the supply voltage is normal or has dropped.
The criteria voltage to be used can be selected from 8 levels using SVDS2–SVDS0. Furthermore, two types
of 8-voltage combinations for 3.0 V and 1.5 V supply voltages are available and either one can be selected
using SVDCHG. Set SVDCHG to "1" when 3.0 V (typ.) supply voltage is used or to "0" when 1.5 V (typ.)
supply voltage is used.
Table 4.13.2.1 lists the criteria voltages.
Table 4.13.2.1 Criteria voltage
SVDS2
1
0
SVDS1
1
0
1
0
SVDS0
1
0
1
0
1
0
1
0
1.5 V system (SVDCHG = "0")
1.50
1.40
1.30
1.25
1.20
1.15
1.10
1.05
Criteria voltage (V)
3.0 V system (SVDCHG = "1")
2.90
2.70
2.40
2.10
2.00
1.90
1.80
1.70
When the SVDON register is set to "1", source voltage or external voltage detection by the SVD circuit is
executed. As soon as the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the
SVD circuit goes off.
To obtain a stable detection result, the SVD circuit must be on for at least 1 msec. So, to obtain the SVD
detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 1 msec minimum
3. Set SVDON to "0"
4. Read SVDDT
When the SVD circuit is on, the IC draws a large current, so keep the SVD circuit off unless it is.
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