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参数资料
| 型号： | S1C7XXXF00E10C |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| 文件页数： | 46/196页 |
| 文件大小： | 1650K |
| 代理商： | S1C7XXXF00E10C |
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2 REGISTERS
2-2
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
2.3 Processor Status Register (PSR)
Symbol
PSR
Size
8 bits
Initial value
0x00
Register name
Processor Status Register
R/W
R/W
The Processor Status Register (hereinafter referred to as the “PSR”) is an 8-bit register for storing the internal status
of the processor.
The PSR stores the internal status of the processor when the status has been changed by instruction execution. It is
referenced in arithmetic operations or branch instructions, and therefore constitutes an important internal status in
program composition. The PSR does not allow the program to directly alter its contents except for the IE bit.
As the PSR affects program execution, whenever an interrupt occurs, the PSR is saved to the stack, except for de-
bug interrupts, to maintain the PSR value. The IE flag (bit 4) in it is cleared to 0. The reti instruction is used to
return from interrupt handling, and the PSR value is restored from the stack at the same time.
IL[2:0]
7
6
5
IE
4
C
3
V
2
Z
1
N
0
Initial value
PSR
Figure 2.3.1 Processor Status Register (PSR)
IL[2:0] (bits 7–5): Interrupt Level
These bits indicate the priority levels of the processor interrupts. Maskable interrupt requests are accepted only
when their priority levels are higher than that set in the IL bit field. When an interrupt request is accepted, the
IL bit field is set to the priority level of that interrupt, and all interrupt requests generated thereafter with the
same or lower priority levels are masked, unless the IL bit field is set to a different level or the interrupt handler
routine is terminated by the reti instruction.
IE (bit 4): Interrupt Enable
This bit controls maskable external interrupts by accepting or disabling them. When IE bit = 1, the processor
enables maskable external interrupts. When IE bit = 0, the processor disables maskable external interrupts.
When an interrupt is accepted, the PSR is saved to the stack and this bit is cleared to 0. However, the PSR is not
saved to the stack for debug interrupts, nor is this bit cleared to 0.
C (bit 3): Carry
This bit indicates a carry or borrow. More specifically, this bit is set to 1 when, in an add or subtract instruction
in which the result of operation is handled as an unsigned 16-bit integer, the execution of the instruction result-
ed in exceeding the range of values representable by an unsigned 16-bit integer, or is reset to 0 when the result
is within the range of said values.
The C flag is set under the following conditions:
(1) When an addition executed by an add instruction resulted in a value greater than the maximum value 0xffff
representable by an unsigned 16-bit integer
(2) When a subtraction executed by a subtract instruction resulted in a value smaller than the minimum value
0x0000 representable by an unsigned 16-bit integer
V (bit 2): OVerflow
This bit indicates that an overflow or underflow occurred in an arithmetic operation. More specifically, this bit
is set to 1 when, in an add or subtract instruction in which the result of operation is handled as a signed 16-bit
integer, the execution of the instruction resulted in an overflow or underflow, or is reset to 0 when the result of
the add or subtract operation is within the range of values representable by a signed 16-bit integer. This flag is
also reset to 0 by executing a logical operation instruction.
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