
7 DETAILS OF INSTRUCTIONS
7-88
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
ld.cf %rd, imm7
Function
Transfer data to the coprocessor and get the flag status
Standard)
co_dout0
← rd, co_dout1 ← imm7, psr(C, V, Z, N) ← co_cvzn
Extension 1) co_dout0
← rd, co_dout1 ← imm20, psr(C, V, Z, N) ← co_cvzn
Extension 2) co_dout0
← rd, co_dout1 ← imm24, psr(C, V, Z, N) ← co_cvzn
Code
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 0 1 0 1
r d
imm7
|
Flag
IL IE
C
V
Z
N
– –
|
Mode
Src:Immediate data (unsigned)
Dst:Register direct %rd = %r0 to %r7
CLK
One cycle
Description (1) Standard
ld.cf
%rd,imm7
; co_dout1 data = imm7
Transfers data set in the rd register and 7-bit immediate imm7 to the coprocessor and gets the
flag status of the coprocessor to the C, V, Z, and N flags in the PSR.
(2) Extension 1
ext
imm13
; = imm20(19:7)
ld.cf
%rd,imm7
; co_dout1 data = imm20, imm7 = imm20(6:0)
The ext instruction extends the immediate to a 20-bit quantity. As a result, data set in the rd
register and 20-bit immediate imm20 are transferred to the coprocessor and the flag status is
loaded to the C, V, Z, and N flags in the PSR.
(3) Extension 2
ext
imm13
; = imm24(31:19)
ext
imm13
; = imm24(18:6)
ld.cf
%rd,imm7
; co_dout1 data = imm24, imm7
← imm24(5:0)
The two ext instructions extend the displacement to a 24-bit quantity. As a result, data set in
the rd register and 24-bit immediate imm24 are transferred to the coprocessor and the flag status
is loaded to the C, V, Z, and N flags in the PSR.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the “d” bit. In this case, extension of the immediate by the ext
instruction cannot be performed.