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参数资料
| 型号： | S1D13600F00A |
| 元件分类： | 显示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封装： | QFP6-64 |
| 文件页数： | 24/29页 |
| 文件大小： | 190K |
| 代理商： | S1D13600F00A |
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S1D13600 Series
1–4
EPSON
Rev. 2.3
CPU Interface
(1) 3.3 V 68XX dedicated CPU Interface.
(2) 8 bit Data are used to transfer Data or Commands.
(3) The rising edge of “
CS” signal is used to execute the Data Transfer.
(4) “DT/
CM” is used for CPU to indicate either Data or Command is on the bus.
(5) “
SLEEP” signal is used to set the chip in Sleep Mode.
(6) No other signals are required for the normal operation.
(7) “
RESET” is used to initialize the chip.
Address Generator for CPU Access
(1) The internal CPU Write Start Address can be set by the command.
(2) After every single CPU Display Data Write Access, the internal CPU Write Address Counter is
increased by one.
Address Generator for Display Refresh
(1) “E” is used to generate the Display Refresh Address.
(2) Address Generator begins when the immediate Frame comes after the CPU Display Data Write
Access occurs or when CPU sets the “Display Data Transfer” command.
(3) Address Generation stops if no CPU Display Data Write Access occurs for two LCD Frame period.
Address Selector
When CPU Display Data Write Access occurs, the internal CPU Write Address is selected to generate
the address for SRAM.
Memory Controller
(1) When CPU Display Data Write Access occurs, Memory Controller stores the data into SRAM.
(2) The Memory Controller begins reading the data stored in the SRAM to transfer to the LCD Module
when the immediate Frame comes after the CPU Display Data Write Access occurs or when CPU sets
the “Display Data Transfer” command.
(3) The Memory Controller stops reading the data from the SRAM if no CPU Display Data Write Access
occurs for two LCD Frame period.
LCD Timing Generator
(1) Local oscillation is directly used to generate “LP” (Horizontal Sync. Pulse), “YD” (Vertical Sync.
Pulse) and “FR” (LCD voltage alternation signal).
(2) The updated data stored in the SRAM is transferred through the Memory Controller and the LCD
Timing Generator to the LCD Module, if the CPU Display Data Write Access occurs or when CPU
sets the “Display Data Transfer” command.
(3) The LCD Timing Generator uses “E” to generate “XSCLU”.
(4) “XSCLU” is automatically controlled by the CPU Display Data Write Access or setting the “Display
Data Transfer” command.
Power Management Unit
(1) Power Management Unit monitors the occurrence of CPU Display Data Write Access, the execution
of the “Display Data Transfer” command, the internal state of LCD Frame period and the “
SLEEP”
signal in order to determine entering to Doze Mode and returning to Active Mode. And this unit also
controls local oscillation.
Test Unit
Test Unit controls test functions of the chip if the chip is in Test Mode.
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相关代理商/技术参数 |
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| S1D13702F00A100 | 功能描述:LCD 驱动器 Organic EL Controller RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
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