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参数资料
| 型号： | S1D13600F00A |
| 元件分类： | 显示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封装： | QFP6-64 |
| 文件页数： | 28/29页 |
| 文件大小： | 190K |
| 代理商： | S1D13600F00A |
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S1D13600 Series
1–8
EPSON
Rev. 2.3
5. PIN DESCRIPTION
Key
C
= CMOS level input
CS
= CMOS level input with hysteresis
COSC
= CMOS level input for an internal oscillation inverter
T
= TTL level input
OX
= CMOS output, x denotes output driver type.
OOSC
= CMOS output for an internal oscillation inverter
PU
= integrated pull-up resistor
PD
= integrated pull-down resistor
CPU Interface
The CPU interface signals are placed on one side of the chip for easy connection to CPU. And the input
levels of all CPU Interface pins are unified with CMOS level to allow easy connection to 3.3 V 68 family
CPUs.
Table 2. CPU Interface Pin Description
Pin Name
Type Pin No.
Drv
Description
Data inputs. The data is captured into an
D [0:7]
I
2…9
C
S1D13600’s input data register by the rising edge
of “
CS”.
In Active Mode, “E” is used to write or read the
E
I
15
C
CPU data to from SRAM and transfer the data
written in the SRAM to the LCD Module.
The rising edge of this signal is used to capture the
CS
I
14
C
state of “D [0:7] and “DT/
CM” into S1D13600.
When “
CS” is HIGH, no data captures occur.
DT/
CM
I13
C
If this signal is HIGH, Data is on the bus. If this
signal is LOW, Command is on the bus.
If this signal is pulled LOW, the chip enters Sleep
Mode. In the Sleep Mode, internal oscillation is
SLEEP
I
11
C
disabled, all of the input signals are masked and all
of the output signals are controlled to inactive
state.
RESET
I10
CS
The active LOW “
RESET” signal from the system
clears all internal registers.
SRAM Interface
The SRAM Interface signals are basically placed on two sides of the chip. The input level of “VD [0:7]”
is met with TTL level to connect with generic 3.3 V SRAMs. And also “VD [0:7]” have integrated pull-
up resistors to eliminate current consumption at the input buffers in Doze Mode.
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