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参数资料
| 型号： | S1D13600F00A |
| 元件分类： | 显示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封装： | QFP6-64 |
| 文件页数： | 29/29页 |
| 文件大小： | 190K |
| 代理商： | S1D13600F00A |
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S1D13600 Series
Rev. 2.3
EPSON
1–9
Table 3. SRAM Interface Pin Description
Pin Name
Type Pin No.
Drv
Description
T
The “VD [0:7]” signals are connected to SRAM’s 8
VD [0:7]
I/O
35…42 O2
bit data. The captured display data in S1D13600
PU
are stored in the SRAM through “VD [0:7]” by the
“VR/
W” signal.
The “VA [0:14]” signals are connected to SRAM’s
VA [0:14]
O
44…58 O2
address lines. “VA [0:14]” generate either CPU
Display Data Write Address or Display Refresh
Address depending upon operation modes.
S1D13600 manages up to 64 kb of SRAM as a
frame buffer memory. S1D13600 is configured to
primarily use two 256 kb SRAMs. “
VCS0” is
VCS [0:1]
O
59, 60
O2
active when 1st 32 kb is selected. “
VCS1” is
active when the rest 32 kb is selected. “
VCS
[0:1]” are connected to SRAM’s chip select inputs
(active LOW). Those signals are inactie (HIGH), if
the chip is in Sleep Mode.
VOE
O34
O2
The “
VOE” signal is connected to SRAM’s data
output enable input.
VR/
W
O43
O2
The “VR/
W” signal is connected to SRAM’s write
strobe input.
LCD Interface
The LCD interface signals are placed on the rest one side of the chip. The output type of all signals is
optimized to drive the Ultra Low Power LCD Module properly.
Pin Name
Type Pin No.
Drv
Description
The “XD [0:7]” signals are connected to the display
data inputs of the LCD Module. During Doze
XD [0:7]
O
24…31 O1
Mode, the signals are driven LOW. “XD [0:7] are
transferred to the LCD Module by the falling edge
of “XSCLU”.
The “XSCLU” signal is connected to the display
data shift clock of the LCD Module. During Doze
XSCLU
O
20
O1
Mode, the signal is driven LOW to force the RAM
integrated Segment Drivers to be in Power Save
Mode.
The “LP” signal is connected to te input, which
drives the data latching pulse of the segment
LP
O
21
O1
drivers and the scanning clock of the common
drivers, of the LCD Module. The “LP” period is
directly generated by the signal which is input
through “OSC1”.
YD
O
22
O1
The “YD” is connected to the frame start pulse
signal of the LCD Module.
FR
O
23
O1
The “FR” signal is connected to the signal which
alternates the LCD voltage in the LCD Module.
DOFF
O
18
O1
This signal outputs LOW if the chip is in Sleep Mode.
Table 4. LCD Interface Pin Description
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