
Epson Research and Development
Page 5
Vancouver Design Center
Register Summary
S1D13A05
Issue Date: 02/01/21
X40A-R-001-01
EXTENDED PANEL REGISTERS
HR-TFT Mode 2 CLS Width Register
REG[A0h]
Default = 0000012Ch
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
CLS Pulse Width bits 8-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 PS1 Rising Edge Register
REG[A4h]
Default = 00000032h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PS1 Rising Edge bits 5-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 PS2 Rising Edge Register
REG[A8h]
Default = 00000064h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PS2 Rising Edge bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 PS2 Toggle Width Register
REG[ACh]
Default = 0000000Ah
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PS2 Toggle Width bits 6-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 PS3 Signal Width Register
REG[B0h]
Default = 00000064h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PS3 Signal Width bits 6-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 REV Toggle Point Register
REG[B4h]
Default = 0000000Ah
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
REV Toggle Point bits 4-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HR-TFT Mode 2 PS1/2 End Register
REG[B8h]
Default = 00000007h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PS1/2 End bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type 2 TFT Configuration Register
REG[BCh]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
POL Type
n/a
AP Pulse Width bits 2-0
n/a
AP Rising Position bits1-0
n/a
VCLK Hold bits 1-0
n/a
VCLK Setup bits 1-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Casio TFT Timing Register
REG[C0h]
Default = 09180E09h
Read/Write
n/a
GPCK Rising Edge to STH Pulse bits 5-0
n/a
GRES Falling Edge to FRP Toggle Point bits 6-0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
GRES Falling Edge to GPCK Rising Edge bits 5-0
n/a
GPCK Rising Edge to GRES Rising Edge bits 5-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type 3 TFT Configuration Register 0
REG[D8h]
Default = 00000000h
Read/Write
POL Toggle Position bits 7-0
OE Pulse Width bits 7-0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OE Rising Edge Position bits 7-0
n/a
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type 3 TFT Configuration Register 1
REG[DCh]
Default = 00000000h
Read/Write
XOEV Falling Edge Position bits 7-0
XOEV Rising Edge Position bits 7-0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CPV Pulse Width bits 7-0
VCOM Toggle Position bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type 3 TFT PCLK Divide Register
REG[E0h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
PCLK2 Divide Rate bits
1-0
PCLK1 Divide Rate bits 3-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0