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参数资料
| 型号： | S80296SA40 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 3/40页 |
| 文件大小： | 1096K |
| 代理商： | S80296SA40 |
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PRELIMINARY
7
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when the bus controller
has a pending external memory cycle. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the
configuration selected through the port configuration registers (P2_MODE, P2_DIR,
and P2_REG). An attempt to change the pin configuration is ignored until the bus-
hold protocol is disabled (WSR.7 is cleared).
The microcontroller can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
BREQ# shares a package pin with P2.3.
CLKOUT
O
Clock Output
Output of the internal clock generator. The CLKOUT frequency is the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7.
CS5:0#
O
Chip-select Lines 0–5
The active-low output CS
x# is asserted during an external memory cycle when the
address to be accessed is in the range programmed for chip select
x or chip select
x+1 if remapping is enabled. If the external memory address is outside the range
assigned to the six chip selects, no chip-select output is asserted and the bus
configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the range FF2000–
FF20FFH.
CS5:0# share package pins with P3.5:0.
EPA3:0
I/O
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels. For high-
speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1
or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared
output pin.
EPA3:0 share package pins with P1.3:0.
EPORT.3:0
I/O
Extended Addressing Port
This is a standard 4-bit, bidirectional port.
EPORT.3:0 share package pins with A19:16.
Table 4. Signal Descriptions (Continued)
Name
Type
Description
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相关代理商/技术参数 |
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| S80296SA50 | 功能描述:IC MPU 16BIT 5V 50MHZ 100QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:80296SA 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| S80296SA-50 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER |
| S80298ECE WAF | 制造商:Intel 功能描述: |
| S802C21S207B | 制造商:C&K Components 功能描述:SWIT SLIDE DPDT TOP SLIDE 20VAC 20VDC 0.4W QC PNL MNT - Bulk 制造商:C&K Components 功能描述:Switch Slide DPDT Top Slide 20VAC 20VDC 0.4VA Quick Connect Panel Mount |
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