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参数资料
| 型号： | S80296SA40 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 4/40页 |
| 文件大小： | 1096K |
| 代理商： | S80296SA40 |
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8
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
EXTINT3:0
I
External Interrupts
These programmable interrupts are controlled by the EXTINT_CON register. This
register controls whether the interrupt is edge-triggered or level-sensitive and
whether a rising edge/high level or falling edge/low level activates the interrupt.
In standby and powerdown modes, asserting the EXTINT
x signal causes the device
to resume normal operation. The interrupt does not need to be enabled, but the pin
must be configured as a special-function input. If the EXTINT
x interrupt is enabled,
the CPU executes the interrupt service routine. Otherwise, the CPU executes the
instruction that immediately follows the command that invoked the power-saving
mode.
In idle mode, asserting any enabled interrupt causes the device to resume normal
operation.
EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with
P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package pin
with P3.7.
HLDA#
O
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result of
an external device asserting HOLD#. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the
configuration selected through the port configuration registers (P2_MODE, P2_DIR,
and P2_REG). An attempt to change the pin configuration is ignored until the bus-
hold protocol is disabled (WSR.7 is cleared).
HLDA# shares a package pin with P2.6.
HOLD#
I
Bus Hold Request
An external device uses this active-low input signal to request control of the bus.
When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can
function only as HOLD#, regardless of the configuration selected through the port
configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change
the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
cleared).
HOLD# shares a package pin with P2.5.
INST
O
Instruction Fetch
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector fetches
and chip configuration byte reads. INST is low during internal memory fetches.
Table 4. Signal Descriptions (Continued)
Name
Type
Description
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相关代理商/技术参数 |
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| S80296SA50 | 功能描述:IC MPU 16BIT 5V 50MHZ 100QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:80296SA 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| S80296SA-50 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER |
| S80298ECE WAF | 制造商:Intel 功能描述: |
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