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参数资料
| 型号： | S80296SA40 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 6/40页 |
| 文件大小： | 1096K |
| 代理商： | S80296SA40 |
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10
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PLLEN2:1
I
Phase-locked Loop 1 and 2 Enable
These input pins enable the on-chip clock multiplier feature and select either the
doubled or the quadrupled clock speed:
PLLEN2
PLLEN1
Mode
0
1x mode; PLL disabled; f = F
XTAL
1
0
1
2x mode; PLL enabled; f = 2F
XTAL
1
0
Reserved
1
4x mode; PLL enabled; f = 4F
XTAL
1
CAUTION: This reserved combination causes the device to enter an unsupported
test mode.
PWM2:0
O
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
PWM2:0 share package pins with P4.2:0.
RD#
O
Read
Read-signal output to external memory. RD# is asserted during external memory
reads.
READY
I
Ready Input
This active-high input can be used to insert wait states in addition to those
programmed in chip configuration byte 0 (CCB0) and the bus control
x register
(BUSCON
x).
CCB0 is programmed with the minimum number of wait states (0, 5, 10, 15) for an
external fetch of CCB1, and BUSCON
x is programmed with the minimum number of
wait states (0–15) for all external accesses to the address range assigned to the
chip-select
x channel.
If the programmed number of wait states is greater than zero and READY is low
when this programmed number of wait states is reached, additional wait states are
added until READY is pulled high. If the programmed number of wait states is equal
to zero, hold the READY pin high. Programming the number of wait states equal to
zero and holding the READY pin low produces unpredictable results.
RESET#
I/O
Reset
A level-sensitive reset input to, and an open-drain system reset output from, the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-
down transistor connected to the RESET# pin for 16 state times.
In the powerdown, standby, and idle modes, asserting RESET# causes the
microcontroller to reset and return to normal operating mode. If the phase-locked
loop (PLL) clock circuitry is enabled, you must hold RESET# low for at least 2 ms to
allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled.
After a reset, the first instruction fetch is from FF2080H.
Table 4. Signal Descriptions (Continued)
Name
Type
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S80296SA50 | 功能描述:IC MPU 16BIT 5V 50MHZ 100QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:80296SA 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| S80296SA-50 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER |
| S80298ECE WAF | 制造商:Intel 功能描述: |
| S802C21S207B | 制造商:C&K Components 功能描述:SWIT SLIDE DPDT TOP SLIDE 20VAC 20VDC 0.4W QC PNL MNT - Bulk 制造商:C&K Components 功能描述:Switch Slide DPDT Top Slide 20VAC 20VDC 0.4VA Quick Connect Panel Mount |
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