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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
24
The External Memory System Must Meet These Specifications (Continued)
T
LLGX
BUSWIDTH Hold after ALE/ADV# Low
T
OSC
ns
T
LHDV
ALE/ADV# High to Input Data Valid
3T
OSC – 55
ns
T
AVDV
Address Valid to Input Data Valid
3T
OSC – 55
ns
T
RLDV
RD# Active to Input Data Valid
T
OSC – 30
ns
T
RHDZ
End of RD# to Input Data Float
T
OSC
ns
T
RXDX
Data Hold after RD# Inactive
0
ns
The 8XC196MH will Meet These Specifications
T
XHLH
XTAL1 Rising Edge to ALE Rising
20
110
ns
T
XHLL
XTAL1 Rising Edge to ALE Falling
20
110
ns
T
LHLH
ALE/ADV# Cycle Time
4T
OSC
ns
T
LHLL
ALE/ADV# High Period
T
OSC – 10
T
OSC + 10
ns
T
AVLH
Address Valid to ALE/ADV# High
T
OSC – 17
ns
T
AVLL
Address Valid to ALE/ADV# Low
T
OSC – 17
ns
T
LLAX
Address Hold after ALE/ADV# Low
T
OSC – 40
ns
T
LLRL
ALE/ADV# Low to RD# Low
T
OSC – 30
ns
T
RLRH
RD# Low Period
T
OSC – 5
T
OSC + 25
ns
T
RHLH
RD# High to ALE/ADV# High
T
OSC
T
OSC + 25
ns
T
RLAZ
RD# Low to Address Float
5
ns
T
LLWL
ALE/ADV# Low to WR# Low
T
OSC – 10
ns
T
QVWH
Data Valid before WR# High
T
OSC – 23
ns
T
WLWH
WR# Low Period
T
OSC – 30
ns
T
WHQX
Data Hold after WR# High
T
OSC – 25
ns
T
WHLH
WR# High to ALE/ADV# High
T
OSC – 10
T
OSC + 15
ns
T
WHBX
BHE#, INST Hold after WR# High
T
OSC – 10
ns
T
WHAX
A15:8 Hold after WR# High
T
OSC – 30
ns
T
RHBX
BHE#, INST Hold after RD# High
T
OSC – 10
ns
T
RHAX
A15:8 Hold after RD# High
T
OSC – 30
ns
Table 11. AC Timing Definitions (1) (Continued)
Symbol
Parameter
Min
Max
Units
Notes
NOTES:
1.
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F
OSC = 16 MHz.
2.
Exceeding the maximum specification causes additional wait states.
3.
If wait states are used, add 2T
OSC × n, where n = number of wait states.
4.
Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5.
Assuming back-to-back bus cycles.
6.
8-bit bus only.