参数资料
型号: S83C196MH
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封装: SHRINK, QFP-80
文件页数: 9/41页
文件大小: 1547K
代理商: S83C196MH
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
17
READY
I
Ready Input. This active-high input signal is used to
lengthen external memory cycles for slow memory by
generating wait states.
When READY is high, CPU operation continues in a normal
manner. If READY is low, the memory controller inserts wait
states until the READY signal goes high or until the number
of wait states is equal to the number programmed into the
chip configuration register.
READY is ignored for all internal memory accesses.
P5.6
RESET#
I/O
Reset. Reset input to and open-drain output from the chip. A
falling edge on RESET# initiates the reset process. When
RESET# is first asserted, the chip turns on a pull-down
transistor connected to the RESET pin for 16 state times.
This function can also be activated by execution of the RST
instruction. In the powerdown and idle modes, asserting
RESET# causes the chip to reset and return to normal
operating mode. RESET# is a level-sensitive input.
RXD1
RXD0
I/O
Receive Serial Data 0 and 1. In modes 1, 2, and 3, RXD0
and 1 are used to receive serial port data. In mode 0, they
function as either inputs or open-drain outputs for data.
P1.3
P1.1
SCLK1#
SCLK0#
I/O
Synchronous Clock Pin 0 and 1. In mode 4, these are the
bidrectional, shift clock signals that synchronize the serial
data transfer. Data is transferred 8 bits at a time with the LSB
first. The DIR bit (SP_CON
x.7) controls the direction of
SCLK
x signal.
DIR = 0
The internal shift clock is output on SCLK
x.
DIR = 1
An external shift clock is input on SCLK
x.
P2.7/BCLK1
P2.1/BCLK0
T1CLK
I
External Clock. External clock for timer 1. Timer 1
increments (or decrements) on both rising and falling edges
of T1CLK. Also used in conjunction with T1DIR for
quadrature counting mode.
P0.6/ACH6/PMODE.2
T1DIR
I
Timer 1 External Direction. External direction (up/down) for
timer 1. Timer 1 increments when T1DIR is high and
decrements when it is low. Also used in conjunction with
T1CLK for quadrature counting mode.
P0.7/ACH7/PMODE.3
TXD1
TXD0
O
Transmit Serial Data 0 and 1. In serial I/O modes 1, 2, and
3, TXD0 and 1 are used to transmit serial port data. In mode
0, they are used as the serial clock output.
P1.2
P1.0
V
CC
PWR
Digital Supply Voltage. Connect each V
CC pin to the digital
supply voltage.
V
PP
PWR
Programming Voltage. Set to 12.5 V when programming the
on-chip OTPROM. Also the timing pin for the “return from
power-down” circuit.
Table 7. Signal Descriptions (Continued)
Signal
Name
Type
Description
Multiplexed
With
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