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参数资料
| 型号： | S83C196MH |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | SHRINK, QFP-80 |
| 文件页数： | 5/41页 |
| 文件大小： | 1547K |
| 代理商： | S83C196MH |
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
13
BHE#
O
Byte High Enable. During 16-bit bus cycles, this active-low
output signal is asserted for word reads and writes and for
high-byte reads and writes to external memory. BHE#
indicates that valid data is being transferred over the upper
half of the system address/data bus.
BHE#, in conjunction with A0, selects the memory byte to be
accessed:
BHE#
A0
Byte(s) Accessed
0
both bytes
0
1
high byte only
1
0
low byte only
P5.5/WRH#
BUSWIDTH
I
Bus Width. When enabled in the chip configuration register,
this active-high input signal dynamically selects the bus width
of the bus cycle in progress. When BUSWIDTH is high, a 16-
bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus
cycle occurs. BUSWIDTH is active during a CCR fetch.
P5.7
COMP3
COMP2
COMP1
COMP0
O
Event Processor Array (EPA) Compare Pins. These
signals are the output of the EPA compare modules. These
pins are multiplexed with other signals and may be
configured as standard I/O.
P2.3
P2.6/CPVER
P2.5/PACT#
P2.4/AINC#
CPVER
O
Cumulative Program Verification. This active-high output
signal indicates whether any verify errors have occurred
since the device entered programming mode. CPVER
remains high until a verify error occurs, at which time it is
driven low. Once an error occurs, CPVER remains low until
the device exits programming mode. When high, CPVER
indicates that all locations have programmed correctly since
the device entered programming mode.
P2.6/COMP2
EA#
I
External Access. This active-low input signal directs
memory accesses to on-chip or off-chip memory. If EA# is
low, the memory access is off-chip. If EA# is high and the
memory address is within 2000H–2FFFH, the access is to
on-chip ROM or OTPROM. Otherwise, an access with EA#
high is to off-chip memory.
EA# is sampled only on the rising edge of RESET#.
If EA# = V
EA on the rising edge of RESET#, the device enters
the programming mode selected by PMODE.3:0.
For devices without ROM, EA# must be tied low.
—
EPA1
EPA0
I/O
Event Processor Array (EPA) Input/Output pins. These
are the high-speed input/output pins for the EPA
capture/compare modules. These pins are multiplexed with
other signals and may be configured as standard I/O.
P2.2/PROG#
P2.0/PVER
Table 7. Signal Descriptions (Continued)
Signal
Name
Type
Description
Multiplexed
With
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PDF描述 |
|---|---|
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
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| S83C51FC-IA44 | 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQCC44 |
| S83C51FA-4B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S83C198 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER |
| S83C198-16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Microcontroller |
| S83C51FA-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S83C51FA-24 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S83C51FA-33 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
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