C167CS-4R
C167CS-L
Data Sheet
61
V2.2, 2001-08
Sample time and conversion time of the C167CS’s A/D Converter are programmable.
Table 14 should be used to calculate the above timings.
The limit values for
fBC must not be exceeded when selecting ADCTC.
Converter Timing Example:
Assumptions:
fCPU = 25 MHz (i.e. tCPU = 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.
Basic clock
fBC
=
fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns.
Sample time
tS
=
tBC × 8 = 1280 ns.
Conversion time
tC
=
tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 s.
5) As the default basic clock after reset is f
BC = fCPU / 4 the ADC’s prescaler (ADCTC) must be programmed to
a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a
proper reset calibration. This corresponds to minimum 300 instructions (worst case: external MUX bus with
maximum waitstates). This is required for
fCPU > 33 MHz and is recommended for fCPU > 25 MHz.
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7) Not 100% tested, guaranteed by design and characterization.
8) During the sample time the input capacitance C
AIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
tS.
After the end of the sample time
tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time
tS depend on programming and can be taken from Table 14. Table 14
A/D Converter Computation Table
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock
fBC
ADCON.13|12
(ADSTC)
Sample time
tS
00
fCPU / 4
00
tBC × 8
01
fCPU / 2
01
tBC × 16
10
fCPU / 16
10
tBC × 32
11
fCPU / 8
11
tBC × 64