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| 型号： | SAB-C167CS-LMCA |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, MQFP-144 |
| 文件页数： | 72/84页 |
| 文件大小： | 1082K |
| 代理商： | SAB-C167CS-LMCA |
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C167CS-4R
C167CS-L
Data Sheet
70
V2.2, 2001-08
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage.
1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a
demultiplexed bus without MTTC waitstate this delay is zero.
3) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT,
it must fulfill
tc27 in order to be safely synchronized.
Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge
of the corresponding command (RD or WR).
4) READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
5) If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first
valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current
cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a
multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.
Table 19
READY Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input setup time to CLKOUT rising edge
Valid for: READY input
tc25 CC
12
–
ns
Input hold time after CLKOUT rising edge
Valid for: READY input
tc26 CC
0
–
ns
Asynchronous READY input low time3)
tc27 CC
tc5 + tc25 –
ns
相关PDF资料 |
PDF描述 |
|---|---|
| SAB-C167CS-4R33M | 16-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP144 |
| SAB-C167CS-4RM | 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP144 |
| SAK-C167CS-LM | 16-BIT, 25 MHz, MICROCONTROLLER, PQFP144 |
| SAB-C167CS-4R40M | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP144 |
| SAK-C167CS-4R40M | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SABC167CSLMCA+ | 制造商:Infineon Technologies AG 功能描述: |
| SABC167CSLMCA+X | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 3.3V/5V 144-Pin MQFP |
| SAB-C167SR-L33M | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller |
| SAB-C167SR-LM | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:16-Bit CMOS Single-Chip Microcontroller |
| SABC167SR-LM | 制造商:Infineon Technologies AG 功能描述:MCU 16-bit C166 CISC/RISC ROMLess 5V 144-Pin MQFP |
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