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参数资料
| 型号： | SC16C550IB48,128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件页数： | 15/52页 |
| 文件大小： | 639K |
| 代理商： | SC16C550IB48,128 |
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Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
22 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = ‘0’): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = ‘1’): Set and enable the interrupt in a block mode operation.
The transmit interrupt is set when the transmit FIFO has at least one empty location.
The receive interrupt is set when the receive FIFO lls to the programmed trigger
level. However, the FIFO continues to ll regardless of the programmed level until the
FIFO is full. RXRDY remains a logic 0 as long as the FIFO ll level is above the
programmed trigger level.
7.3.2
FIFO mode
Table 10:
FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5-4
FCR[5]
(MSB),
FCR[4]
(LSB)
Not used; set to 00.
3
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C550 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the rst character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C550 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C550IN40 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550IN40,112 | 功能描述:IC UART SINGLE W/FIFO 40-DIP RoHS:是 类别:集成电路 (IC) >> 接口 - UART（通用异步接收器/发送器） 系列:- 标准包装:250 系列:- 特点:* 通道数:2，DUART FIFO's:16 字节 规程:RS232，RS485 电源电压:2.25 V ~ 5.5 V 带并行端口:- 带自动流量控制功能:是 带IrDA 编码器/解码器:是 带故障启动位检测功能:是 带调制解调器控制功能:是 带CMOS:是 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:托盘 其它名称:XR16L2551IM-F-ND |
| SC16C554 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554B | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554B_10 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
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