- 您现在的位置：买卖IC网 > PDF目录98078 > SC16C550IB48,128 (NXP SEMICONDUCTORS) 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 PDF资料下载
参数资料
| 型号： | SC16C550IB48,128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件页数： | 21/52页 |
| 文件大小： | 639K |
| 代理商： | SC16C550IB48,128 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
28 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C550 and
the CPU.
Table 19:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the transmit FIFO and transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.
相关PDF资料 |
PDF描述 |
|---|---|
| SC16C654IB64,128 | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| SC16C654IA68,512 | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| SC18005CQ | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| SC18IS600IBS,151 | I2C BUS CONTROLLER, PQCC24 |
| SC18IS600IBS | I2C BUS CONTROLLER, PQCC24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C550IN40 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550IN40,112 | 功能描述:IC UART SINGLE W/FIFO 40-DIP RoHS:是 类别:集成电路 (IC) >> 接口 - UART（通用异步接收器/发送器） 系列:- 标准包装:250 系列:- 特点:* 通道数:2，DUART FIFO's:16 字节 规程:RS232，RS485 电源电压:2.25 V ~ 5.5 V 带并行端口:- 带自动流量控制功能:是 带IrDA 编码器/解码器:是 带故障启动位检测功能:是 带调制解调器控制功能:是 带CMOS:是 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:托盘 其它名称:XR16L2551IM-F-ND |
| SC16C554 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554B | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554B_10 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
发布紧急采购，3分钟左右您将得到回复。