参数资料
型号: SC16IS752IPW,112
厂商: NXP Semiconductors
文件页数: 21/60页
文件大小: 0K
描述: IC UART DUAL 12C/SPI 28TSSOP
产品培训模块: Stand-Alone UARTs
I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 51
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
产品目录页面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名称: 568-4016-5
935279292112
SC16IS752IPW
SC16IS752IPW-ND
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
28 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.9 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the host. It also indicates when a control input
from the modem changes state. Table 21 shows Modem Status Register bit settings per
channel.
Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.
8.10 Scratchpad Register (SPR)
The SC16IS752/SC16IS762 provides a temporary data register to store 8 bits of user
information.
Table 21.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (active HIGH, logical 1). If GPIO6 or GPIO2 is selected as CD
modem pin through IOControl register bit 1 or bit 2, the state of CD pin
can be read from this bit. This bit is the complement of the CD input.
Reading IOState bit 6 or bit 2 does not reflect the true state of CD pin.
6
MSR[6]
RI (active HIGH, logical 1). If GPIO7 or GPIO3 is selected as RI modem
pin through IOControl register bit 1 or bit 2, the state of RI pin can be
read from this bit. This bit is the complement of the RI input. Reading
IOState bit 7 or bit 3 does not reflect the true state of RI pin.
5
MSR[5]
DSR (active HIGH, logical 1). If GPIO4 or GPIO0 is selected as DSR
modem pin through IOControl register bit 1 or bit 2, the state of DSR pin
can be read from this bit. This bit is the complement of the DSR input.
Reading IOState bit 4 or bit 0 does not reflect the true state of DSR pin.
4
MSR[4]
CTS (active HIGH, logical 1). This bit is the complement of the CTS
input.
3MSR[3]
CD. Indicates that CD input has changed state. Cleared on a read.
2MSR[2]
RI. Indicates that RI input has changed state from LOW to HIGH.
Cleared on a read.
1MSR[1]
DSR. Indicates that DSR input has changed state. Cleared on a read.
0MSR[0]
CTS. Indicates that CTS input has changed state. Cleared on a read.
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