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| 型号： | SC18IM700IPW |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 连接器件 |
| 英文描述： | Master I?C-bus controller with UART interface |
| 封装： | SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html& |
| 文件页数： | 12/22页 |
| 文件大小： | 118K |
| 代理商： | SC18IM700IPW |
SC18IM700_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 August 2007
12 of 22
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
9.2.2.4
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
DD
.
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
9.2.3
Programmable I/O pins state register (IOState)
When read, this register returns the actual state of all I/O pins. When written, each
register bit will be transferred to the corresponding I/O pin programmed as output.
9.2.4
I
2
C-bus address register (I2CAdr)
The contents of the register represents the device’s own I
2
C-bus address. The most
significant bit corresponds to the first bit received from the I
2
C-bus after a START
condition. A logic 1 in I2CAdr corresponds to a HIGH level on the I
2
C-bus, and a logic 0
corresponds to a LOW level on the I
2
C-bus. The least significant bit is not used, but should
be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I
2
C-bus device address used by the bus master.
9.2.5
I
2
C-bus clock rates (I2CClk)
This register determines the serial clock frequency. The various serial rates are shown in
Table 7
. The frequency can be determined using the following formula:
I2CClkH determines the SCL HIGH period, and I2CClkL determines the SCL LOW period.
Fig 16. Open-drain output configuration
002aab883
V
SS
pin latch data
GPIO pin
glitch rejection
input data
Table 6.
Bit
7:0
IOState - Programmable I/O pins state register (address 0x04h) bit description
Symbol
Description
IOLevel
Set the logic level on the output pins.
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
Read this register returns states of all pins.
bit frequency
I2CClkH
6
I2CClkL
+
2
(
)
×
-------------------------------------------------------------------
=
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| SC18IM700IPW,112 | 功能描述:UART 接口集成电路 CTRL I2C W/UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC18IM700IPW,128 | 功能描述:UART 接口集成电路 UART-MASTER I2C RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC18IM700IPW/S8HP | 功能描述:IC CTRL I2CW/UART 16TSSOP 制造商:nxp usa inc. 系列:- 零件状态:在售 协议:I2C 功能:控制器 接口:UART 标准:- 电压 - 电源:2.4 V ~ 3.6 V 电流 - 电源:9mA 工作温度:-40°C ~ 85°C 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:16-TSSOP 标准包装:1 |
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| SC18IM700IPW-F | 功能描述:UART 接口集成电路 UART-MASTER I2C BRIDGE W/GPIO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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