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参数资料
| 型号： | SC18IM700IPW |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 连接器件 |
| 英文描述： | Master I?C-bus controller with UART interface |
| 封装： | SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html& |
| 文件页数： | 13/22页 |
| 文件大小： | 118K |
| 代理商： | SC18IM700IPW |
SC18IM700_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 August 2007
13 of 22
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
Remark:
The numbers used in the formulas are in decimal, but the numbers to program
I2CClkH and I2CClkL are in hex.
9.2.6
I
2
C-bus time-out (I2CTO)
The time-out register is used to determine the maximum time that SCL is allowed to be
LOW before the I
2
C-bus state machine is reset.
When the I
2
C-bus interface is running, I2CTO is loaded after each I
2
C-bus state transition.
The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1
will enable the time-out function. The time-out period can be calculated as follows:
The time-out value may vary, and it is an approximate value.
9.2.7
I
2
C-bus status register (I2CStat)
This register reports the I
2
C-bus transmit and receive frame status, whether the frame
transmits correctly or not.
Table 7.
I2CClk
(I2CClkH + I2CClkL)
10 (minimum)
15
25
30
50
60
100
I
2
C-bus clock frequency
I
2
C-bus clock frequency
369 kHz
246 kHz
147 kHz
123 kHz
74 kHz
61 kHz
37 kHz
Table 8.
Bit
7:1
0
I2CTO - I
2
C-bus time-out register (address 0x09h) bit description
Symbol
Description
TO[7:1]
time-out value
TE
enable/disable time-out function
logic 0 = disable
logic 1 = enable
time
-
out period
----------------------------------------------
57600
onds
sec
=
Table 9.
Bit 7
1
1
1
1
I
2
C-bus status
Bit 6
Bit 5
1
1
1
1
1
1
1
1
Bit 4
1
1
1
1
Bit 3
0
0
0
1
Bit 2
0
0
0
0
Bit 1
0
0
1
0
Bit 0
0
1
0
0
I
2
C-bus status description
I2C_OK
I2C_NACK_ON_ADDRESS
I2C_NACK_ON_DATA
I2C_TIME_OUT
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