参数资料
型号: SC18IM700IPW
厂商: NXP Semiconductors N.V.
元件分类: 连接器件
英文描述: Master I?C-bus controller with UART interface
封装: SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html&
文件页数: 16/22页
文件大小: 118K
代理商: SC18IM700IPW
SC18IM700_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 August 2007
16 of 22
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
12. Dynamic characteristics
Table 12.
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
= 2.4 V to 3.6 V;
T
amb
=
40
°
C to +85
°
C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
.
Symbol
Parameter
Conditions
I
2
C-bus timing characteristics
Standard mode
I
2
C-bus
Min
0
4.7
Fast mode
I
2
C-bus
Min
0
1.3
Unit
Max
100
-
Max
400
-
f
SCL
t
BUF
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
kHz
μ
s
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
4.0
4.7
4.0
0
-
-
-
250
4.7
4.0
-
-
-
-
-
-
-
0.6
0.6
0.6
0
-
-
-
100
1.3
0.6
-
-
-
-
-
-
-
μ
s
μ
s
μ
s
ns
μ
s
μ
s
μ
s
ns
μ
s
μ
s
μ
s
μ
s
ns
0.6
0.6
0.6
-
-
-
0.3
1
50
0.6
0.6
0.6
-
-
-
0.3
0.3
50
LOW-level
HIGH-level
t
SU;DAT
t
LOW
t
HIGH
t
f
t
r
t
SP
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
Fig 17. I
2
C-bus timing
SDA
SCL
002aab271
t
f
S
Sr
P
S
t
HD;STA
t
LOW
t
r
t
SU;DAT
t
f
t
HD;DAT
t
HIGH
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
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