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参数资料
| 型号： | SC18IM700IPW |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 连接器件 |
| 英文描述： | Master I?C-bus controller with UART interface |
| 封装： | SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC18IM700IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html& |
| 文件页数： | 15/22页 |
| 文件大小： | 118K |
| 代理商： | SC18IM700IPW |
SC18IM700_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 August 2007
15 of 22
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
11. Static characteristics
[1]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2]
See
Table 10 “Limiting values”
for steady state (non-transient) limits on I
OL
or I
OH
. If I
OL
/I
OH
exceeds the test condition, V
OL
/V
OH
may
exceed the related specification.
[3]
Pin capacitance is characterized but not tested.
[4]
Measured with GPIO in quasi-bidirectional mode.
[5]
Measured with GPIO in high-impedance mode.
[6]
GPIO in quasi-bidirectional mode with weak pull-up (applies to all GPIO pins with pull-ups). Does not apply to open-drain pins.
[7]
GPIO pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when V
I
is approximately 2 V.
Table 11.
V
DD
= 2.4 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
I
DD
supply current
Static characteristics
Conditions
V
DD
= 3.6 V
Operating mode; f = 7.3728 MHz
Idle mode; f = 7.3728 MHz
Power-down mode (sleep);
GPIO0 to GPIO7 as inputs;
inputs at V
DD
Min
Typ
[1]
Max
Unit
-
-
-
9
3.25
50
15
5
70
mA
mA
μ
A
V
POR
V
th(HL)
power-on reset voltage
negative-goingthreshold
voltage
LOW-level input voltage
positive-going threshold
voltage
HIGH-level input voltage
LOW-level output
voltage
-
0.22V
DD
-
0.4V
DD
0.2
-
V
V
except SCL, SDA
V
IL
V
th(LH)
SCL, SDA only
except SCL, SDA
0.5
-
-
0.6V
DD
0.3V
DD
0.7V
DD
V
V
V
IH
V
OL
SCL, SDA only
I
OL
= 20 mA
I
OL
= 3.2 mA
I
OH
=
20 mA; Push-pull mode;
GPIO3 to GPIO7
I
OH
=
3.2 mA; Push-pull mode;
GPIO0 to GPIO2
I
OH
=
20 mA; quasi-bidirectional
mode; all GPIOs
0.7V
DD
[2]
-
-
0.6
0.2
-
5.5
1.0
0.3
-
V
V
V
V
[2]
-
V
OH
HIGH-level output
voltage
0.8V
DD
V
DD
0.7 V
DD
0.4 -
V
V
DD
0.3 V
DD
0.2 -
V
C
io
I
IL
I
LI
I
T(HL)
input/output capacitance
LOW-level input current
input leakage current
negative-going transition
current
internal pull-up
resistance on pin
RESET
[3]
-
-
-
-
-
15
80
10
450
pF
μ
A
μ
A
μ
A
logic 0; all ports; V
I
= 0.4 V
all ports; V
I
= V
IL
or V
IH
logic 1-to-0; all ports; V
I
= 2.0 V at
V
DD
= 3.6 V
[4]
-
[5]
-
[6][7]
30
R
RESET_N(int)
10
-
30
k
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