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参数资料
| 型号： | SC202MLTRT |
| 厂商： | Semtech |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | CONVERTER DC/DC 3.3V OUT 500MA |
| 标准包装： | 1 |
| 系列： | SC202 |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 2.9V |
| 电压 - 输入（最大）： | 5.5V |
| Voltage - Output 1： | 0.8 ~ 3.3 V |
| 电流 - 输出（最大）： | 500mA |
| 电源（瓦） - 制造商系列： | 1.65W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 13-VFQFN 裸露焊盘 |
| 尺寸/尺寸： | 0.12" L x 0.10" W x 0.04" H（3.0mm x 2.5mm x 1.0mm） |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 电源（瓦特）- 最大： | 1.65W |
| 其它名称： | SC202MLDKR |
NOT RECOMMENDED FOR NEW DESIGN
Applications Information (continued)
SC202
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IN and
GND pins. Table 3 lists recommended input capacitor
options from different manufacturers.
Table 3 — Recommended Input Capacitors
3. Use a ground plane referenced to the GND pin. Use
several vias to connect to the component side ground
to further reduce noise and interference on sensitive
circuit nodes.
4. Route the output voltage feedback/sense trace
(connected to the SNS pin) away from the LX node
as shown in Figure 3 to minimize noise and magnetic
interference.
5. Minimize the resistance from the OUT and GND pins
Manufacturer
Part Nunber
Murata
GRM188R60J475K
Murata
GRM188R60J106K
Taiyo Yuden
JMK107BJ475KA
Value
(μF)
4.7±10%
10±10%
4.7±10%
Type
X5R
X5R
X5R
Rated
Voltage
(VDC)
6.3
6.3
6.3
Dimensions
LxWxH (mm)
Case Size
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
6. The two smaller exposed pads on this package should
not be connected to any traces. The area beneath
these two pads must be kept clear so that they do
not make electrical contact with any traces, including
ground.
TDK
C1608X5R0J475KT
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
These pads should not
be electrically
connected to the PCB.
CTL2
CTL1
IN
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
C IN
CTL0
CTL3
PCB top-layer for the SC202 and supporting components.
Specified layout rules must be followed since the layout is
critical for achieving the performance specified in the
Electrical Characteristics table. Poor layout can degrade
the performance of the DC-DC converter and can contrib-
ute to EMI problems, ground bounce, and resistive voltage
losses. Poor regulation and instability can also result.
The following guidelines are recommended for designing
3.5mm
C OUT
GND
OUT
3.8mm
SC202
LX
(no
connection
needed)
SNS
a PCB layout:
1. C IN should be placed as close to the IN and GND pins
as possible. This capacitor provides a low impedance
Figure 3 — Recommended PCB Layout
loop for the pulsed currents present at the buck
converter’s input. Use short wide traces to minimize
trace impedance. This will also minimize EMI and
input voltage ripple by localizing the high frequency
current pulses.
2. C OUT should be connected as closely as possible to the
OUT pin.
16
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