参数资料
| 型号： | SC470ITSTRT |
| 厂商： | Semtech |
| 文件页数： | 15/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 14-TSSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 电源电压： | 5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC470ITSDKR |
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NOT RECOMMENDED FOR NEW DESIGN
SC470
POWER MANAGEMENT
Application Information (Cont.)
This means that the ratio is less than the worst-case
U1
EN/PSV
TON
SC470
BST
DH
OVP threshold (worst-case in this case is the lowest
threshold), then the direct drive (simplest) method may
Open Drain Signal
R5
49k9
C5
56p
0402
VOUT
R3
20k0
0402
VOUT
VCCA
FB
LX
ILIM
VDDP
be used. Of course the indirect drive method may also
be used if desired.
Low = 1.2V
0402
High = 1.0V
R7
20k0
0402
PGD
VSSA
DL
PGND
If:
Figure 4: Dynamic Voltage Switching Using Direct
V OUT ( HIGH )
V OUT ( LOW )
> 1 . 16
Drive Method (V OUT(HIGH) /V OUT(LOW) < 1.16 only)
Another option is to switch using an external discrete
MOSFET, as shown in Figure 5.
This means that the ratio is greater than the worst-case
OVP threshold, therefore we automatically need to slew
the rate of change, and the indirect drive method must
be used.
U1
SC470
If using the indirect drive method, the goal is to slow
R8
pull-up
R5
0402
49k9
C5
56p
0402
VOUT
R3
20k0
0402
EN/PSV
TON
VOUT
VCCA
FB
BST
DH
LX
ILIM
VDDP
down the gate drive for the transition from V OUT(HIGH) to
V OUT(LOW) , which is when the external MOSFET is turned
off. The pull-up resistor, pull-down resistor and gate
capacitor can be selected as follows:
PGD
DL
Open Drain Signal
Low = 1.0V
High = 1.2V
R9
C11
Q3
R7
20k0
0402
VSSA
PGND
1) V GATE must be below the gate threshold voltage of the
MOSFET in order to ensure that it can be turned off (see
Figure 6):
Figure 5: Dynamic Voltage Switching Using Indirect
Drive Method
The problem with the external MOSFET method is that
the drain-gate capacitance, c DG , can cause the output
voltage to go even higher when the MOSFET is first turned
off (which should make the output voltage drop). This is
because the gate going low causes the drain to go low
2) The RC time constant of R9 and C11 should be at
least 4 times greater than the typical Over-Voltage Fault
Delay Time of 5μs to avoid V OUT rising prior to falling.
3) V PULLUP must be high enough to turn the MOSFET on.
VPULLUP
R8
pull-up
momentarily due to c DG , which in turn causes V FB to go
low, making the output rise. The extra R9 and C11 in the
gate drive for the MOSFET are there to slow down the
R9
VGATE
C11
Q3
R 9 ? V PU LLU P
( R 8 + R 9 )
< V GS ( TH )
slew rate of the gate voltage, thus avoiding this problem.
Determining what circuit to use depends upon the ratio
between V OUT(HIGH) and V OUT(LOW) , since the goal is to avoid
inadvertently tripping the over-voltage protection.
If:
Figure 6: Ensuring Q3 Will Turn Off
V OU T ( H IGH )
V OU T ( LOW )
< 1 . 16
? 2005 Semtech Corp.
15
www.semtech.com
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