参数资料
| 型号： | SC470ITSTRT |
| 厂商： | Semtech |
| 文件页数： | 17/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 14-TSSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 电源电压： | 5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC470ITSDKR |
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NOT RECOMMENDED FOR NEW DESIGN
POWER MANAGEMENT
Application Information (Cont.)
Layout Guidelines - TSSOP-14 as an example:
SC470
VBAT
5VSUS
5VSUS
VBAT
D1
SOD323
R1
R2
U1
SC470
C1 0.1uF
1M
0402
10R
0402
1
EN/PSV
BST
14
0603
Q1
IRF7811AV
C2
C3
C4
2
TON
DH
13
2n2/50V
0402
0u1/25V
0603
10u/25V
1210
VOUT
3
VOUT
LX
12
L1
2u2
VOUT SWITCH (1)
R5 49k9
0402
C5
56p
0402
R3
20k0
0402
4
5
VCCA
FB
ILIM
VDDP
11
10
R4 7k87
0402
Q2
FDS6676S
R6 0R (2)
+
C6
220u/25m
7343
+
VOUT
C7
220u/25m
7343
PGOOD
6
PGD
DL
9
0402
C9
C8
R7
20k0
0402
C10
7
VSSA
PGND
8
1uF
0603
1nF
1uF
0402
0603
N OTE S
(1) driv en by an open drain wit h no pullup. LOW = 1. 2V out, F LOATI N G = 1V out .
(2) R 6 is not required but aids keeping VSSA s eparate f rom PGN D ex c ept where des ired in lay out.
VBAT = 8V to 20V
VOUT = 1.2V or 1.0V @ 6A
Figure 8: Reference Design For Dynamic Output Switching
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All
components that are referenced to VSSA should connected to it locally at the chip. VSSA should connect to power
ground at the output capacitor(s) only .
The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run
them in a “quiet layer” if possible. VSSA may be separated from PGND using a zero Ohm resistor (that will be placed
at the bottom of the output capacitors) to aid in net separation.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and
connected directly to them on the same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the
current limit resistor located at the device.
We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in
more detail.
? 2005 Semtech Corp.
17
www.semtech.com
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